/** Publish PEI core memory @return EFI_SUCCESS The PEIM initialized successfully. **/ EFI_STATUS PublishPeiMemory ( VOID ) { EFI_STATUS Status; EFI_PHYSICAL_ADDRESS MemoryBase; UINT64 MemorySize; UINT64 LowerMemorySize; if (mBootMode == BOOT_ON_S3_RESUME) { MemoryBase = PcdGet32 (PcdS3AcpiReservedMemoryBase); MemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize); } else { LowerMemorySize = GetSystemMemorySizeBelow4gb (); // // Determine the range of memory to use during PEI // MemoryBase = PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize); MemorySize = LowerMemorySize - MemoryBase; if (MemorySize > SIZE_64MB) { MemoryBase = LowerMemorySize - SIZE_64MB; MemorySize = SIZE_64MB; } } // // Publish this memory to the PEI Core // Status = PublishSystemMemory(MemoryBase, MemorySize); ASSERT_EFI_ERROR (Status); return Status; }
VOID MemMapInitialization ( VOID ) { // // Create Memory Type Information HOB // BuildGuidDataHob ( &gEfiMemoryTypeInformationGuid, mDefaultMemoryTypeInformation, sizeof(mDefaultMemoryTypeInformation) ); // // Add PCI IO Port space available for PCI resource allocations. // BuildResourceDescriptorHob ( EFI_RESOURCE_IO, EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED, 0xC000, 0x4000 ); // // Video memory + Legacy BIOS region // AddIoMemoryRangeHob (0x0A0000, BASE_1MB); if (!mXen) { UINT32 TopOfLowRam; TopOfLowRam = GetSystemMemorySizeBelow4gb (); // // address purpose size // ------------ -------- ------------------------- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) // 0xFC000000 gap 44 MB // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB // 0xFED00000 HPET 1 KB // 0xFED00400 gap 111 KB // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ? BASE_2GB : TopOfLowRam, 0xFC000000); AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); } AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); } }
/** Peform Memory Detection @return EFI_SUCCESS The PEIM initialized successfully. **/ EFI_PHYSICAL_ADDRESS MemDetect ( ) { EFI_STATUS Status; EFI_PHYSICAL_ADDRESS MemoryBase; UINT64 MemorySize; UINT64 LowerMemorySize; UINT64 UpperMemorySize; DEBUG ((EFI_D_ERROR, "MemDetect called\n")); // // Determine total memory size available // LowerMemorySize = GetSystemMemorySizeBelow4gb (); UpperMemorySize = GetSystemMemorySizeAbove4gb (); // // Determine the range of memory to use during PEI // MemoryBase = PcdGet32 (PcdOvmfMemFvBase) + PcdGet32 (PcdOvmfMemFvSize); MemorySize = LowerMemorySize - MemoryBase; if (MemorySize > SIZE_64MB) { MemoryBase = LowerMemorySize - SIZE_64MB; MemorySize = SIZE_64MB; } // // Publish this memory to the PEI Core // Status = PublishSystemMemory(MemoryBase, MemorySize); ASSERT_EFI_ERROR (Status); // // Create memory HOBs // AddMemoryBaseSizeHob (MemoryBase, MemorySize); AddMemoryRangeHob (BASE_1MB, MemoryBase); AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); MtrrSetMemoryAttribute (BASE_1MB, MemoryBase + MemorySize - BASE_1MB, CacheWriteBack); MtrrSetMemoryAttribute (0, BASE_512KB + BASE_128KB, CacheWriteBack); if (UpperMemorySize != 0) { AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); MtrrSetMemoryAttribute (BASE_4GB, UpperMemorySize, CacheWriteBack); } return MemoryBase + MemorySize; }
/** Peform Memory Detection for QEMU / KVM **/ STATIC VOID QemuInitializeRam ( VOID ) { UINT64 LowerMemorySize; UINT64 UpperMemorySize; DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__)); // // Determine total memory size available // LowerMemorySize = GetSystemMemorySizeBelow4gb (); UpperMemorySize = GetSystemMemorySizeAbove4gb (); if (mBootMode != BOOT_ON_S3_RESUME) { // // Create memory HOBs // AddMemoryRangeHob (BASE_1MB, LowerMemorySize); AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); } MtrrSetMemoryAttribute (BASE_1MB, LowerMemorySize - BASE_1MB, CacheWriteBack); MtrrSetMemoryAttribute (0, BASE_512KB + BASE_128KB, CacheWriteBack); if (UpperMemorySize != 0) { if (mBootMode != BOOT_ON_S3_RESUME) { AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); } MtrrSetMemoryAttribute (BASE_4GB, UpperMemorySize, CacheWriteBack); } }
VOID MemMapInitialization ( VOID ) { // // Create Memory Type Information HOB // BuildGuidDataHob ( &gEfiMemoryTypeInformationGuid, mDefaultMemoryTypeInformation, sizeof(mDefaultMemoryTypeInformation) ); // // Add PCI IO Port space available for PCI resource allocations. // BuildResourceDescriptorHob ( EFI_RESOURCE_IO, EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED, PcdGet64 (PcdPciIoBase), PcdGet64 (PcdPciIoSize) ); // // Video memory + Legacy BIOS region // AddIoMemoryRangeHob (0x0A0000, BASE_1MB); if (!mXen) { UINT32 TopOfLowRam; UINT64 PciExBarBase; UINT32 PciBase; UINT32 PciSize; TopOfLowRam = GetSystemMemorySizeBelow4gb (); PciExBarBase = 0; if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { // // The MMCONFIG area is expected to fall between the top of low RAM and // the base of the 32-bit PCI host aperture. // PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress); ASSERT (TopOfLowRam <= PciExBarBase); ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); PciBase = (UINT32)(PciExBarBase + SIZE_256MB); } else { PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; } // // address purpose size // ------------ -------- ------------------------- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) // 0xFC000000 gap 44 MB // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB // 0xFED00000 HPET 1 KB // 0xFED00400 gap 111 KB // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // PciSize = 0xFC000000 - PciBase; AddIoMemoryBaseSizeHob (PciBase, PciSize); PcdSet64 (PcdPciMmio32Base, PciBase); PcdSet64 (PcdPciMmio32Size, PciSize); AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); // // Note: there should be an // // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); // // call below, just like the one above for RCBA. However, Linux insists // that the MMCONFIG area be marked in the E820 or UEFI memory map as // "reserved memory" -- Linux does not content itself with a simple gap // in the memory map wherever the MCFG ACPI table points to. // // This appears to be a safety measure. The PCI Firmware Specification // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory // [...]". (Emphasis added here.) // // Normally we add memory resource descriptor HOBs in // QemuInitializeRam(), and pre-allocate from those with memory // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area // is most definitely not RAM; so, as an exception, cover it with // uncacheable reserved memory right here. // AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB, EfiReservedMemoryType); } AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); } }
VOID MemMapInitialization ( VOID ) { // // Create Memory Type Information HOB // BuildGuidDataHob ( &gEfiMemoryTypeInformationGuid, mDefaultMemoryTypeInformation, sizeof(mDefaultMemoryTypeInformation) ); // // Add PCI IO Port space available for PCI resource allocations. // BuildResourceDescriptorHob ( EFI_RESOURCE_IO, EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED, 0xC000, 0x4000 ); // // Video memory + Legacy BIOS region // AddIoMemoryRangeHob (0x0A0000, BASE_1MB); if (!mXen) { UINT32 TopOfLowRam; UINT32 PciBase; TopOfLowRam = GetSystemMemorySizeBelow4gb (); if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { // // A 3GB base will always fall into Q35's 32-bit PCI host aperture, // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets // the RAM below 4 GB exceed it. // PciBase = BASE_2GB + BASE_1GB; ASSERT (TopOfLowRam <= PciBase); } else { PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; } // // address purpose size // ------------ -------- ------------------------- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) // 0xFC000000 gap 44 MB // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB // 0xFED00000 HPET 1 KB // 0xFED00400 gap 111 KB // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // AddIoMemoryRangeHob (PciBase, 0xFC000000); AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); } AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); } }