/*----------------------------------------------------------------------------------------*/ STATIC BOOLEAN PcieClkPmCheckDeviceCapability ( IN PCI_ADDR Device, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 MaxFunc; UINT8 CurrentFunc; UINT8 PcieCapPtr; UINT32 Value; MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { Device.Address.Function = CurrentFunc; if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader); if (PcieCapPtr == 0) { return FALSE; } GnbLibPciRead ( Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), AccessWidth32, &Value, StdHeader ); if ((Value & BIT18) == 0) { return FALSE; } } } return TRUE; }
/*----------------------------------------------------------------------------------------*/ VOID STATIC PcieClkPmEnableOnDevice ( IN PCI_ADDR Device, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 MaxFunc; UINT8 CurrentFunc; AGESA_STATUS AgesaStatus; AgesaStatus = AGESA_UNSUPPORTED; if (PcieClkPmCheckDeviceCapability (Device, StdHeader)) { MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { Device.Address.Function = CurrentFunc; if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { AgesaStatus = AgesaGnbOemCallout (StdHeader, AGESA_GNB_PCIE_CLK_REQ, &Device); if (AgesaStatus == AGESA_SUCCESS) { IDS_HDT_CONSOLE (GNB_TRACE, " Enable Clock Power Managment for Device = %d:%d:%d\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function ); PcieClkPmEnableOnFunction (Device, StdHeader); } } } } }
/** * Check if GFX controller fused off * * * @param[in] StdHeader Standard configuration header * @retval TRUE Gfx controller present and available */ BOOLEAN GfxLibIsControllerPresent ( IN AMD_CONFIG_PARAMS *StdHeader ) { return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader); }
/** * Check if IOMMU unit present and enabled * * * * * @param[in] GnbHandle Gnb handle * @param[in] StdHeader Standard configuration header * */ BOOLEAN GnbCheckIommuPresentTN ( IN GNB_HANDLE *GnbHandle, IN AMD_CONFIG_PARAMS *StdHeader ) { if (GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 0, 2, 0), StdHeader)) { return TRUE; } return FALSE; }
STATIC VOID excel950_fun5 ( IN PCI_ADDR Device, IN PCIE_ASPM_TYPE Aspm, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 MaxFunc; UINT8 CurrentFunc; MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { Device.Address.Function = CurrentFunc; if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { excel950_fun4 (Device, Aspm, StdHeader); } } }
/*----------------------------------------------------------------------------------------*/ VOID PcieProgramCommClkCfgOnDevice ( IN PCI_ADDR Device, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 MaxFunc; UINT8 CurrentFunc; MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { Device.Address.Function = CurrentFunc; if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { PcieProgramCommClkCfgOnFunction (Device, StdHeader); } } }
AGESA_STATUS GfxEnableGmmAccessV5 ( IN OUT GFX_PLATFORM_CONFIG *Gfx ) { UINT32 Value; GNB_HANDLE *GnbHandle; GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); ASSERT (GnbHandle != NULL); // GmmBase should be 0 before enable. ASSERT (GnbHandle->GmmBase == 0); if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { IDS_ERROR_TRAP; return AGESA_ERROR; } // Check if base address for GMM allocated by reading D1F0x24 Graphics Memory Mapped Base Address Gfx->GmmBase = 0; GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x24, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); Gfx->GmmBase |= (Value & 0xfffffff0); if (Gfx->GmmBase == 0) { IDS_ERROR_TRAP; return AGESA_ERROR; } // Check if base address for FB allocated GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); if ((Value & 0xfffffff0) == 0) { IDS_ERROR_TRAP; return AGESA_ERROR; } //Push CPU MMIO pci config to S3 script GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); // Turn on memory decoding on GFX to enable access to GMM register space GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); //Push iGPU pci config to S3 script GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); GnbHandle->GmmBase = Gfx->GmmBase; return AGESA_SUCCESS; }
AGESA_STATUS GfxEnableGmmAccess ( IN OUT GFX_PLATFORM_CONFIG *Gfx ) { UINT32 Value; if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { IDS_ERROR_TRAP; return AGESA_ERROR; } // Check if base address for GMM allocated GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx)); if (Gfx->GmmBase == 0) { IDS_ERROR_TRAP; return AGESA_ERROR; } // Check if base address for FB allocated GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); if ((Value & 0xfffffff0) == 0) { IDS_ERROR_TRAP; return AGESA_ERROR; } //Push CPU MMIO pci config to S3 script GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); // Turn on memory decoding on APC to enable access to GMM register space if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); //Push APC pci config to S3 script GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); } // Turn on memory decoding on GFX to enable access to GMM register space GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); //Push iGPU pci config to S3 script GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); return AGESA_SUCCESS; }
/*----------------------------------------------------------------------------------------*/ STATIC VOID PcieClkPmEnableOnDevice ( IN PCI_ADDR Device, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 MaxFunc; UINT8 CurrentFunc; if (PcieClkPmCheckDeviceCapability (Device, StdHeader)) { MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0; for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) { Device.Address.Function = CurrentFunc; if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) { IDS_HDT_CONSOLE (GNB_TRACE, " Enable Clock Power Managment for Device = %d:%d:%d\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function ); PcieClkPmEnableOnFunction (Device, StdHeader); } } } }