AGESA_STATUS GfxInitSsid ( IN GFX_PLATFORM_CONFIG *Gfx ) { AGESA_STATUS Status; UINT32 TempData; PCI_ADDR IgpuAddress; PCI_ADDR HdaudioAddress; Status = AGESA_SUCCESS; TempData = 0; IgpuAddress = Gfx->GfxPciAddress; HdaudioAddress = Gfx->GfxPciAddress; HdaudioAddress.Address.Function = 1; // Set SSID for internal GPU if (UserOptions.CfgGnbIGPUSSID != 0) { GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx)); } else { GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); } // Set SSID for internal HD Audio if (UserOptions.CfgGnbHDAudioSSID != 0) { GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx)); } else { GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx)); GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx)); } return Status; }
VOID PcieForceCompliance ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, AccessWidth32, 0xffffffff, 0x1 << DxF0x88_EnterCompliance_OFFSET, GnbLibGetHeader (Pcie) ); } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) { PciePortRegisterWriteField ( Engine, DxF0xE4_xC0_ADDRESS, DxF0xE4_xC0_StrapForceCompliance_OFFSET, DxF0xE4_xC0_StrapForceCompliance_WIDTH, 0x1, FALSE, Pcie ); } }
/*----------------------------------------------------------------------------------------*/ VOID PcieRetrain ( IN PCI_ADDR Function, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 PcieCapPtr; UINT32 Value; PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); Value = BIT27; if (PcieCapPtr != 0) { GnbLibPciRMW ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER), AccessS3SaveWidth32, ~(UINT32) (BIT5), BIT5, StdHeader ); IDS_HDT_CONSOLE (GNB_TRACE, " PcieRetrain link on Device = %d:%d:%d\n", Function.Address.Bus, Function.Address.Device, Function.Address.Function); do { GnbLibPciRead ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER), AccessS3SaveWidth32, &Value, StdHeader); } while ((Value & BIT27) != 0); } }
VOID NbInitOnPowerOnRecovery ( IN PCI_ADDR NbPciAddress, IN AMD_CONFIG_PARAMS *StdHeader ) { UINTN Index; // Init NBCONFIG for (Index = 0; Index < (sizeof (NbPciInitRecoveryTable) / sizeof (NB_REGISTER_RECOVERY_ENTRY)); Index++) { GnbLibPciRMW ( NbPciAddress.AddressValue | NbPciInitRecoveryTable[Index].Reg, AccessWidth32, NbPciInitRecoveryTable[Index].Mask, NbPciInitRecoveryTable[Index].Data, StdHeader ); } // Init MISCIND for (Index = 0; Index < (sizeof (NbMiscInitRecoveryTable) / sizeof (NB_REGISTER_RECOVERY_ENTRY)); Index++) { GnbLibPciIndirectRMW ( NbPciAddress.AddressValue | D0F0x60_ADDRESS, NbMiscInitRecoveryTable[Index].Reg | IOC_WRITE_ENABLE, AccessWidth32, NbMiscInitRecoveryTable[Index].Mask, NbMiscInitRecoveryTable[Index].Data, StdHeader ); } return; }
VOID PcieCompletionTimeout ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS, AccessWidth32, 0xffffffff, 0x6 << DxF0x80_CplTimeoutValue_OFFSET, GnbLibGetHeader (Pcie) ); if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { PciePortRegisterWriteField ( Engine, DxF0xE4_x20_ADDRESS, DxF0xE4_x20_TxFlushTlpDis_OFFSET, DxF0xE4_x20_TxFlushTlpDis_WIDTH, 0x0, TRUE, Pcie ); } }
VOID PcieLinkSetSlotCap ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS, AccessWidth32, 0xffffffff, 1 << DxF0x58_SlotImplemented_OFFSET, GnbLibGetHeader (Pcie) ); GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS, AccessWidth32, 0xffffffff, 1 << DxF0x3C_IntPin_OFFSET, GnbLibGetHeader (Pcie) ); }
AGESA_STATUS GfxEnableGmmAccess ( IN OUT GFX_PLATFORM_CONFIG *Gfx ) { UINT32 Value; if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { IDS_ERROR_TRAP; return AGESA_ERROR; } // Check if base address for GMM allocated GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx)); if (Gfx->GmmBase == 0) { IDS_ERROR_TRAP; return AGESA_ERROR; } // Check if base address for FB allocated GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); if ((Value & 0xfffffff0) == 0) { IDS_ERROR_TRAP; return AGESA_ERROR; } //Push CPU MMIO pci config to S3 script GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); // Turn on memory decoding on APC to enable access to GMM register space if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) { GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); //Push APC pci config to S3 script GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); } // Turn on memory decoding on GFX to enable access to GMM register space GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); //Push iGPU pci config to S3 script GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); return AGESA_SUCCESS; }
VOID GfxFmDisableController ( IN AMD_CONFIG_PARAMS *StdHeader ) { GnbLibPciRMW ( MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS), AccessS3SaveWidth32, 0xffffffff, 1 << D0F0x7C_ForceIntGFXDisable_OFFSET, StdHeader ); }
SCAN_STATUS STATIC PcieClkPmCallback ( IN PCI_ADDR Device, IN OUT GNB_PCI_SCAN_DATA *ScanData ) { SCAN_STATUS ScanStatus; PCIE_DEVICE_TYPE DeviceType; ScanStatus = SCAN_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, " PcieClkPmCallback for Device = %d:%d:%d\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function ); ScanStatus = SCAN_SUCCESS; DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); switch (DeviceType) { case PcieDeviceRootComplex: case PcieDeviceDownstreamPort: GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); GnbLibPciScanSecondaryBus (Device, ScanData); break; case PcieDeviceUpstreamPort: PcieClkPmEnableOnDevice (Device, ScanData->StdHeader); GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); GnbLibPciScanSecondaryBus (Device, ScanData); ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; break; case PcieDeviceEndPoint: case PcieDeviceLegacyEndPoint: PcieClkPmEnableOnDevice (Device, ScanData->StdHeader); ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; break; default: break; } return ScanStatus; }
AGESA_STATUS GfxInitSview ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; GFX_PLATFORM_CONFIG *Gfx; UINT32 OriginalCmdReg; IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Enter\n"); AgesaStatus = AGESA_SUCCESS; Status = GfxLocateConfigData (StdHeader, &Gfx); AGESA_STATUS_UPDATE (Status, AgesaStatus); if (Status == AGESA_SUCCESS) { if (GfxLibIsControllerPresent (StdHeader)) { if (!GfxFmIsVbiosPosted (Gfx)) { GFX_VBIOS_IMAGE_INFO VbiosImageInfo; LibAmdMemCopy (&VbiosImageInfo.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); VbiosImageInfo.ImagePtr = NULL; VbiosImageInfo.GfxPciAddress = Gfx->GfxPciAddress; VbiosImageInfo.Flags = GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST; GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, &OriginalCmdReg, StdHeader); GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xff, BIT1 | BIT2 | BIT0, StdHeader); Status = AgesaGetVbiosImage (0, &VbiosImageInfo); if (Status == AGESA_SUCCESS && VbiosImageInfo.ImagePtr != NULL) { GfxLibCopyMemToFb (VbiosImageInfo.ImagePtr, 0, (*((UINT8*) VbiosImageInfo.ImagePtr + 2)) << 9, Gfx); } else { GfxFmDisableController (StdHeader); AgesaStatus = AGESA_ERROR; } GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0x00, OriginalCmdReg, StdHeader); } } } IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Exit [0x%x]\n", AgesaStatus); return AgesaStatus; }
/** * Retrain link * * * @param[in] CurrentEngine Pointer to engine config descriptor * @param[in] Pcie Pointer to global PCIe configuration * */ VOID STATIC PcieTrainingRetrainLink ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { GnbLibPciRMW ( CurrentEngine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, AccessWidth32, (UINT32) ~DxFxx68_RetrainLink_MASK, 1 << DxFxx68_RetrainLink_OFFSET, GnbLibGetHeader (Pcie) ); PcieTrainingSetPortStateV2 (CurrentEngine, LinkStateDetecting, TRUE, Pcie); }
VOID STATIC PcieTrainingSuccess ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0); PcieTrainingSetPortStateV2 (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); GnbLibPciRMW ( CurrentEngine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, AccessWidth32, (UINT32) ~DxFxx68_LinkBWManagementStatus_MASK, 1 << DxFxx68_LinkBWManagementStatus_OFFSET, GnbLibGetHeader (Pcie) ); }
/*----------------------------------------------------------------------------------------*/ STATIC VOID PcieClkPmEnableOnFunction ( IN PCI_ADDR Function, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 PcieCapPtr; PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); if (PcieCapPtr != 0) { GnbLibPciRMW ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER), AccessS3SaveWidth32, (UINT32)~(BIT8), BIT8, StdHeader ); } }
/*----------------------------------------------------------------------------------------*/ VOID PcieProgramCommClkCfgOnFunction ( IN PCI_ADDR Function, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 PcieCapPtr; PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); if (PcieCapPtr != 0) { IDS_HDT_CONSOLE (GNB_TRACE, " Program Common Clock configuration for Device = %d:%d:%d\n", Function.Address.Bus, Function.Address.Device, Function.Address.Function); GnbLibPciRMW ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER), AccessS3SaveWidth32, ~(UINT32) (BIT6), BIT6, StdHeader ); } }
VOID PcieNbAspmEnable ( IN PCI_ADDR Function, IN PCIE_ASPM_TYPE Aspm, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 PcieCapPtr; PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader); if (PcieCapPtr != 0) { GnbLibPciRMW ( Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) , AccessS3SaveWidth8, ~(UINT32)(BIT0 | BIT1), Aspm, StdHeader ); } }
AGESA_STATUS GfxEnableGmmAccessV5 ( IN OUT GFX_PLATFORM_CONFIG *Gfx ) { UINT32 Value; GNB_HANDLE *GnbHandle; GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); ASSERT (GnbHandle != NULL); // GmmBase should be 0 before enable. ASSERT (GnbHandle->GmmBase == 0); if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) { IDS_ERROR_TRAP; return AGESA_ERROR; } // Check if base address for GMM allocated by reading D1F0x24 Graphics Memory Mapped Base Address Gfx->GmmBase = 0; GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x24, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); Gfx->GmmBase |= (Value & 0xfffffff0); if (Gfx->GmmBase == 0) { IDS_ERROR_TRAP; return AGESA_ERROR; } // Check if base address for FB allocated GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx)); if ((Value & 0xfffffff0) == 0) { IDS_ERROR_TRAP; return AGESA_ERROR; } //Push CPU MMIO pci config to S3 script GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); // Turn on memory decoding on GFX to enable access to GMM register space GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx)); //Push iGPU pci config to S3 script GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx)); GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx)); GnbHandle->GmmBase = Gfx->GmmBase; return AGESA_SUCCESS; }
/** * Deassert GPIO port reset. * * Transition to LinkStateResetDuration state * * @param[in] CurrentEngine Pointer to engine config descriptor * @param[in] Pcie Platform configuration * */ VOID PcieTrainingDeassertResetV2 ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIe_SLOT_RESET_INFO ResetInfo; ResetInfo.ResetControl = DeassertSlotReset; ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId; LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie)); AgesaPcieSlotResetControl (0, &ResetInfo); GnbLibPciRMW ( CurrentEngine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, AccessWidth32, (UINT32) ~DxFxx68_LinkDis_MASK, 0 << DxFxx68_LinkDis_OFFSET, GnbLibGetHeader (Pcie) ); PcieTrainingSetPortStateV2 (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie); }
/** * Set state for all engines connected to same reset ID * * * * @param[in] Engine Pointer to engine config descriptor * @param[in, out] Buffer Pointer to Reset Id * @param[in] Pcie Pointer to global PCIe configuration * */ VOID PcieSetResetStateOnEnginesV2 ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 ResetId; ResetId = *(UINT8 *)Buffer; if (Engine->Type.Port.PortData.ResetId == ResetId && !PcieConfigIsSbPcieEngine (Engine)) { PcieTrainingSetPortStateV2 (Engine, LinkStateResetDuration, TRUE, Pcie); GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, AccessWidth32, (UINT32) ~DxFxx68_LinkDis_MASK, 1 << DxFxx68_LinkDis_OFFSET, GnbLibGetHeader (Pcie) ); } }
VOID STATIC PcieLinkInitHotplugCZ ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { DxFxxE4_xB5_STRUCT DxFxxE4_xB5; UINT32 Value; if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { DxFxxE4_xB5.Value = PciePortRegisterRead (Engine, DxFxxE4_xB5_ADDRESS, Pcie); DxFxxE4_xB5.Field.LcEhpRxPhyCmd = 0x3; DxFxxE4_xB5.Field.LcEhpTxPhyCmd = 0x3; DxFxxE4_xB5.Field.LcEnhancedHotPlugEn = 0x1; DxFxxE4_xB5.Field.LcRcvrDetEnOverride = 0; PciePortRegisterWrite ( Engine, DxFxxE4_xB5_ADDRESS, DxFxxE4_xB5.Value, TRUE, Pcie ); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET, D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH, 0x5, TRUE, Pcie ); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0118_ADDRESS), D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_OFFSET, D0F0xE4_CORE_0118_RCVR_DET_CLK_ENABLE_WIDTH, 0x1, TRUE, Pcie ); } if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxFxx6C_ADDRESS, AccessS3SaveWidth32, 0xffffffff, 1 << DxFxx6C_HotplugCapable_OFFSET, GnbLibGetHeader (Pcie) ); PciePortRegisterWriteField ( Engine, DxFxxE4_x20_ADDRESS, DxFxxE4_x20_TxFlushTlpDis_OFFSET, DxFxxE4_x20_TxFlushTlpDis_WIDTH, 0x0, TRUE, Pcie ); PciePortRegisterWriteField ( Engine, DxFxxE4_x70_ADDRESS, DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET, DxFxxE4_x70_RxRcbCplTimeoutMode_WIDTH, 0x1, FALSE, Pcie ); } if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) { Value = 1; } else { Value = 0; } PciePortRegisterWriteField ( Engine, DxFxxE4_x10_ADDRESS, DxFxxE4_x10_NativePmeEn_OFFSET, DxFxxE4_x10_NativePmeEn_WIDTH, Value, TRUE, Pcie ); }
VOID PcieLinkInitHotplug ( IN PCIe_ENGINE_CONFIG *Engine, IN PCIe_PLATFORM_CONFIG *Pcie ) { DxF0xE4_xB5_STRUCT DxF0xE4_xB5; if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) { DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie); DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3; DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3; DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1; PciePortRegisterWrite ( Engine, DxF0xE4_xB5_ADDRESS, DxF0xE4_xB5.Value, TRUE, Pcie ); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS), D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET, D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH, 0x5, TRUE, Pcie ); PcieRegisterWriteField ( PcieConfigGetParentWrapper (Engine), WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS), D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET, D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH, 0x1, TRUE, Pcie ); } if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { GnbLibPciRMW ( Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, AccessS3SaveWidth32, 0xffffffff, 1 << DxF0x6C_HotplugCapable_OFFSET, GnbLibGetHeader (Pcie) ); PciePortRegisterWriteField ( Engine, DxF0xE4_x20_ADDRESS, DxF0xE4_x20_TxFlushTlpDis_OFFSET, DxF0xE4_x20_TxFlushTlpDis_WIDTH, 0x0, TRUE, Pcie ); PciePortRegisterWriteField ( Engine, DxF0xE4_x70_ADDRESS, DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET, DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH, 0x1, FALSE, Pcie ); } }
AGESA_STATUS GnbCableSafeEntry ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS Status; PCIe_PLATFORM_CONFIG *Pcie; PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp]; UINT8 HdpIndex; UINT8 CurrentIndex; GNB_CABLE_SAFE_DATA CableSafeData; BOOLEAN ForceCableSafeOff; IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n"); Status = AGESA_SUCCESS; ForceCableSafeOff = GnbBuildOptions.CfgForceCableSafeOff; IDS_OPTION_HOOK (IDS_GNB_FORCE_CABLESAFE, &ForceCableSafeOff, StdHeader); if (GnbCableSafeIsSupported (StdHeader)) { if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) { DdiEngineList[HdpIndex] = NULL; } LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader); if (!ForceCableSafeOff) { PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE, GnbCableSafeGetConnectorInfoArrayCallback, DdiEngineList, Pcie ); CurrentIndex = 0; for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) { if (DdiEngineList [HdpIndex] != NULL) { CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1; CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex]; IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex); CurrentIndex++; } } } else { GMMx6124_STRUCT GMMx6124; GMMx6124.Value = 0x3F; NbSmuSrbmRegisterWrite (SMU_GMM_TO_FCR (GMMx6124_ADDRESS), &GMMx6124.Value, TRUE, GnbLibGetHeader (Pcie)); GnbLibPciRMW ( MAKE_SBDFO (0, 0, 0x18, 6, D18F6x80_ADDRESS), AccessWidth32, 0xffffffff, (7 << D18F6x80_CableSafeDisAux_3_1_OFFSET) | (7 << D18F6x80_CableSafeDisAux_6_4_OFFSET), GnbLibGetHeader (Pcie) ); } CableSafeData.Config.Enable = 0x1; CableSafeData.Config.DebounceFilter = 0; CableSafeData.Config.SoftPeriod = 0x4; CableSafeData.Config.Unit = 0x1; CableSafeData.Config.Period = 0xf424; NbSmuRcuRegisterWrite ( SMUx0B_x85D0_ADDRESS, (UINT32*) &CableSafeData, sizeof (CableSafeData) / sizeof (UINT32), TRUE, StdHeader ); NbSmuServiceRequest (0x05, TRUE, StdHeader); } else { Status = AGESA_ERROR; } } IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status); return Status; }
AGESA_STATUS NbInitOnPowerOn ( IN GNB_PLATFORM_CONFIG *Gnb ) { UINTN Index; FCRxFF30_0398_STRUCT FCRxFF30_0398; UINT32 Value; // Init NBCONFIG for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { GnbLibPciRMW ( Gnb->GnbPciAddress.AddressValue | NbPciInitTable[Index].Reg, AccessWidth32, NbPciInitTable[Index].Mask, NbPciInitTable[Index].Data, Gnb->StdHeader ); } // Init MISCIND for (Index = 0; Index < (sizeof (NbMiscInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { GnbLibPciIndirectRMW ( Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS, NbMiscInitTable[Index].Reg | IOC_WRITE_ENABLE, AccessWidth32, NbMiscInitTable[Index].Mask, NbMiscInitTable[Index].Data, Gnb->StdHeader ); } // Init ORB for (Index = 0; Index < (sizeof (NbOrbInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) { GnbLibPciIndirectRMW ( Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS, NbOrbInitTable[Index].Reg | (1 << D0F0x94_OrbIndWrEn_OFFSET), AccessWidth32, NbOrbInitTable[Index].Mask, NbOrbInitTable[Index].Data, Gnb->StdHeader ); } if (!GfxLibIsControllerPresent (Gnb->StdHeader)) { FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) | (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) | (1 << FCRxFF30_0398_SoftResetUvd_OFFSET); NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader); } Value = 0; for (Index = 0x8400; Index <= 0x85AC; Index = Index + 4) { NbSmuRcuRegisterWrite ( (UINT16) Index, &Value, 1, FALSE, Gnb->StdHeader ); } NbSmuRcuRegisterWrite ( 0x9000, &Value, 1, FALSE, Gnb->StdHeader ); NbSmuRcuRegisterWrite ( 0x9004, &Value, 1, FALSE, Gnb->StdHeader ); return AGESA_SUCCESS; }
SCAN_STATUS PcieAspmCallback ( IN PCI_ADDR Device, IN OUT GNB_PCI_SCAN_DATA *ScanData ) { SCAN_STATUS ScanStatus; PCIE_ASPM_DATA *PcieAspmData; PCIE_DEVICE_TYPE DeviceType; ScanStatus = SCAN_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmCallback for Device = %d:%d:%d\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function ); PcieAspmData = (PCIE_ASPM_DATA *) ScanData; ScanStatus = SCAN_SUCCESS; DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); switch (DeviceType) { case PcieDeviceRootComplex: case PcieDeviceDownstreamPort: PcieAspmData->DownstreamPort = Device; //PcieExitLatencyData->LinkCount++; GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); //PcieExitLatencyData->LinkCount--; //Pcie ASPM Black List for L0s with HW method change if ((DeviceType == PcieDeviceRootComplex) && (PcieAspmData->AspmL0sBlackList == TRUE)) { IDS_HDT_CONSOLE (GNB_TRACE, " Black List L0s disabled = %d:%d:%d\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function); GnbLibPciIndirectRMW (Device.AddressValue | 0xE0, 0xA0, AccessS3SaveWidth32, 0xfffff0ff, 0, ScanData->StdHeader); } break; case PcieDeviceUpstreamPort: excel950_fun0 ( PcieAspmData->DownstreamPort, Device, PcieAspmData->Aspm, &PcieAspmData->AspmL0sBlackList, ScanData->StdHeader ); GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader); GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData); ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; break; case PcieDeviceEndPoint: case PcieDeviceLegacyEndPoint: excel950_fun0 ( PcieAspmData->DownstreamPort, Device, PcieAspmData->Aspm, &PcieAspmData->AspmL0sBlackList, ScanData->StdHeader ); ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES; break; default: break; } return ScanStatus; }