int HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev) { struct le_pci_softc *lesc = (struct le_pci_softc *)device_get_softc(dev); HAIKU_INTR_REGISTER_STATE; uint16_t value; HAIKU_INTR_REGISTER_ENTER(); /* get current flags */ bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, LE_CSR0); bus_space_barrier(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE); value = bus_space_read_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RDP); /* is there a pending interrupt? */ if (value & LE_C0_INTR) { /* set the new flags, disable interrupts */ bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, LE_CSR0); bus_space_barrier(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE); bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RDP, value & ~LE_C0_INEA); lesc->sc_am79900.lsc.sc_lastisr |= value; } HAIKU_INTR_REGISTER_LEAVE(); return value & LE_C0_INTR; }
static void le_pci_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val) { struct le_pci_softc *lesc = (struct le_pci_softc *)sc; #ifdef __HAIKU__ HAIKU_INTR_REGISTER_STATE; if (port == LE_CSR0) HAIKU_INTR_REGISTER_ENTER(); #endif bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, port); bus_barrier(lesc->sc_rres, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE); bus_write_2(lesc->sc_rres, PCNET_PCI_RDP, val); #ifdef __HAIKU__ if (port == LE_CSR0) HAIKU_INTR_REGISTER_LEAVE(); #endif }
static uint16_t le_pci_rdcsr(struct lance_softc *sc, uint16_t port) { struct le_pci_softc *lesc = (struct le_pci_softc *)sc; #ifdef __HAIKU__ HAIKU_INTR_REGISTER_STATE; uint16_t value; if (port == LE_CSR0) HAIKU_INTR_REGISTER_ENTER(); #endif bus_write_2(lesc->sc_rres, PCNET_PCI_RAP, port); bus_barrier(lesc->sc_rres, PCNET_PCI_RAP, 2, BUS_SPACE_BARRIER_WRITE); #ifndef __HAIKU__ return (bus_read_2(lesc->sc_rres, PCNET_PCI_RDP)); #else value = bus_read_2(lesc->sc_rres, PCNET_PCI_RDP); if (port == LE_CSR0) HAIKU_INTR_REGISTER_LEAVE(); return value; #endif }