ulg
decompress_kernel(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p)
{
output_data = (uch *) output_start;
free_mem_ptr = free_mem_ptr_p;
free_mem_ptr_end = free_mem_ptr_end_p;
disable_watchdog();
arch_decomp_setup();
/* initialize clock */
HAL_CLOCK_INITIALIZE(RTC_PERIOD);
printf("MicroRedBoot v1.4, (c) 2009 DD-WRT.COM (%s REVISION %s)\n", __DATE__,SVN_REVISION);
printf("keep the reset button pushed to enter redboot!\n");
printf("CPU Type: Atheros AR%s\n",get_system_type());
printf("CPU Clock: %dMhz\n", cpu_frequency() / 1000000);
nvram_init();
char *ddboard = nvram_get("DD_BOARD");
if (ddboard)
printf("Board: %s\n", ddboard);
char *resetbutton = nvram_get("resetbutton_enable");
if (resetbutton && !strcmp(resetbutton, "0"))
puts("reset button manual override detected! (nvram var resetbutton_enable=0)\n");
if (resetTouched() || (resetbutton && !strcmp(resetbutton, "0"))) {
puts("Reset Button triggered\nBooting Recovery RedBoot\n");
int count = 5;
while (count--) {
if (!resetTouched()) // check if reset button is unpressed again
break;
udelay(1000000);
}
if (count <= 0) {
puts("reset button 5 seconds pushed, erasing nvram\n");
if (!flashdetect())
flash_erase_nvram(flashsize, NVRAM_SPACE);
}
bootoffset = 0x800004bc;
resettrigger = 0;
puts("loading");
lzma_unzip();
puts("\n\n\n");
return output_ptr;
} else {
flashdetect();
linuxaddr = getLinux();
puts("Booting Linux\n");
resettrigger = 1;
/* important, enable ethernet bus, if the following lines are not initialized linux will not be able to use the ethernet mac, taken from redboot source */
enable_ethernet();
puts("loading");
lzma_unzip();
set_cmdline();
}
}
externC void hal_IRQ_init(void)
{
// No architecture general initialization, but the variant may have
// provided some.
hal_variant_IRQ_init();
// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
// Set max period
HAL_CLOCK_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
}
static void sys_timer_init(void)
{
#ifdef CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF
HAL_CLOCK_INITIALIZE(set_period);
#else
HAL_CLOCK_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
#endif // CYGSEM_REDBOOT_BSP_SYSCALLS_GPROF
cyg_drv_interrupt_create(
CYGNUM_HAL_INTERRUPT_RTC,
0, // Priority - unused
(CYG_ADDRWORD)0, // Data item passed to ISR & DSR
sys_timer_isr, // ISR
sys_timer_dsr, // DSR
&sys_timer_handle, // handle to intr obj
&sys_timer_interrupt ); // space for int obj
cyg_drv_interrupt_attach(sys_timer_handle);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_RTC);
}
void plf_hardware_init(void)
#endif
{
// Any hardware/platform initialization that needs to be done.
// Clear all interrupt sources
HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableClear, 0xFFFF);
#ifndef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
#endif
// FIXME: The line with the thumb check is a hack, allowing
// the farm to run test. Problem is that virtual vector table
// API needs to be ARM/Thumb consistent. Will fix later.
#if !defined(__thumb__) && !defined(CYGPKG_HAL_ARM_INTEGRATOR_ARM9)
// Set up eCos/ROM interfaces
hal_if_init();
#endif
}
void intr_main( void )
{
CYG_INTERRUPT_STATE oldints;
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_RTC, 1,
ISR_DATA, isr, NULL, &intr_handle, &intr);
cyg_drv_interrupt_attach(intr_handle);
HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_RTC);
HAL_ENABLE_INTERRUPTS();
while( ticks < 10 )
{
}
HAL_DISABLE_INTERRUPTS(oldints);
CYG_TEST_PASS_FINISH("HAL interrupt test");
}
void intr_main( void )
{
CYG_INTERRUPT_STATE oldints;
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_RTC, 1,
ISR_DATA, isr, dsr, &intr_handle, &intr);
cyg_drv_interrupt_attach(intr_handle);
HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_RTC);
HAL_ENABLE_INTERRUPTS();
while( ticks < 10 )
{
}
CYG_TEST_CHECK( dsr_ticks == 10, "DSR not called sufficient times");
HAL_DISABLE_INTERRUPTS(oldints);
CYG_TEST_PASS_FINISH("HAL interrupt test");
}
/**
*
* Hardware initialization.
*
* @return none
*
*****************************************************************************/
void hal_hardware_init(void)
{
cyg_uint32 dw_i, dwCPUID;
// -------- Ininializing GIC -------------------------------------------
// Connect GIC to CORE0
dwCPUID = 1;
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR + XSCUGIC_DIST_EN_OFFSET, 0UL);
// For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
//
// 1. The trigger mode in the int_config register
// Only write to the SPI interrupts, so start at 32
//
for (dw_i = 32; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 16) {
//
// Each INT_ID uses two bits, or 16 INT_ID per register
// Set them all to be level sensitive, active HIGH.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_INT_CFG_OFFSET_CALC(dw_i),
0UL);
}
for (dw_i = 0; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 4) {
//
// 2. The priority using int the priority_level register
// The priority_level and spi_target registers use one byte per
// INT_ID.
// Write a default value that can be changed elsewhere.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_PRIORITY_OFFSET_CALC(dw_i),
DEFAULT_PRIORITY);
}
for (dw_i = 32; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 4) {
//
// 3. The CPU interface in the spi_target register
// Only write to the SPI interrupts, so start at 32
//
dwCPUID |= dwCPUID << 8;
dwCPUID |= dwCPUID << 16;
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_SPI_TARGET_OFFSET_CALC(dw_i),
dwCPUID);
}
for (dw_i = 0; dw_i < XSCUGIC_MAX_NUM_INTR_INPUTS; dw_i += 32) {
//
// 4. Enable the SPI using the enable_set register. Leave all
// disabled for now.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR +
XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, dw_i),
0xFFFFFFFFUL);
}
HAL_WRITE_UINT32(XC7Z_SCUGIC_DIST_BASEADDR + XSCUGIC_DIST_EN_OFFSET,
XSCUGIC_EN_INT_MASK);
//
// Program the priority mask of the CPU using the Priority mask register
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_CPU_BASEADDR + XSCUGIC_CPU_PRIOR_OFFSET, 0xF0);
//
// If the CPU operates in both security domains, set parameters in the
// control_s register.
// 1. Set FIQen=1 to use FIQ for secure interrupts,
// 2. Program the AckCtl bit
// 3. Program the SBPR bit to select the binary pointer behavior
// 4. Set EnableS = 1 to enable secure interrupts
// 5. Set EnbleNS = 1 to enable non secure interrupts
//
//
// If the CPU operates only in the secure domain, setup the
// control_s register.
// 1. Set FIQen=1,
// 2. Set EnableS=1, to enable the CPU interface to signal secure interrupts.
// Only enable the IRQ output unless secure interrupts are needed.
//
HAL_WRITE_UINT32(XC7Z_SCUGIC_CPU_BASEADDR + XSCUGIC_CONTROL_OFFSET, 0x07);
#ifdef HAL_PLF_HARDWARE_INIT
// Perform any platform specific initializations
HAL_PLF_HARDWARE_INIT();
#endif
#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
HAL_DCACHE_ENABLE(); // Enable DCache
#endif
#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
HAL_ICACHE_ENABLE(); // Enable ICache
#endif
// Set up eCos/ROM interfaces
hal_if_init();
HAL_CLOCK_INITIALIZE(CYGNUM_HAL_RTC_PERIOD);
#ifdef CYGPKG_HAL_SMP_SUPPORT
cyg_uint32 reg;
/* Disable the distributor */
HAL_READ_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
reg &= ~(0x2);
HAL_WRITE_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
/* Clear pending interrupts */
HAL_WRITE_UINT32(XC7Z_ICD_ICPR0_BASEADDR, 0xffffffff);
HAL_WRITE_UINT32(XC7Z_ICD_ICPR1_BASEADDR, 0xffffffff);
HAL_WRITE_UINT32(XC7Z_ICD_ICPR2_BASEADDR, 0xffffffff);
/* Re-enable the distributor */
HAL_READ_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
reg |= 0x2;
HAL_WRITE_UINT32(XC7Z_ICD_DCR_BASEADDR, reg);
/* Start the cpu */
cyg_hal_smp_init();
hal_interrupt_init_cpu();
cyg_hal_smp_cpu_start_first();
#endif
}
void hal_reset_vsr( void )
{
// Call system init routine. This should do the minimum necessary
// for the rest of the initialization to complete. For example set
// up GPIO, the SRAM, power management etc. This routine is
// usually supplied by the platform HAL. Calls to
// hal_variant_init() and hal_platform_init() later will perform
// the main initialization.
hal_system_init();
// Initialize vector table in base of SRAM.
{
register int i;
#if !defined(CYG_HAL_STARTUP_RAM)
// Only install the exception vectors for non-RAM startup. For
// RAM startup we want these to continue to point to the original
// VSRs, which will belong to RedBoot or GDB stubs.
for( i = 2; i < 15; i++ )
hal_vsr_table[i] = (CYG_ADDRESS)hal_default_exception_vsr;
#endif
// Always point SVC and PENDSVC vectors to our local versions
hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
hal_vsr_table[CYGNUM_HAL_VECTOR_PENDSV] = (CYG_ADDRESS)hal_pendable_svc_vsr;
// For all startup type, redirect interrupt vectors to our VSR.
for( i = CYGNUM_HAL_VECTOR_SYS_TICK ;
i < CYGNUM_HAL_VECTOR_SYS_TICK + CYGNUM_HAL_VSR_MAX;
i++ )
hal_vsr_table[i] = (CYG_ADDRESS)hal_default_interrupt_vsr;
}
#if !defined(CYG_HAL_STARTUP_RAM)
// Ensure that the CPU will use the vector table we have just set
// up.
# if defined(CYGHWR_HAL_CORTEXM_M3)
// On M3 parts, the NVIC contains a vector table base register. We
// program this to relocate the vector table base to the base of
// SRAM.
HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR,
CYGARC_REG_NVIC_VTOR_TBLOFF(0)|
CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM );
# else
# error Unknown SRAM/VECTAB remap mechanism
# endif
// Use SVC to switch our state to thread mode running on the PSP.
// We don't need to do this for RAM startup since the ROM code
// will have already done it.
hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;
__asm__ volatile( "swi" );
hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
#endif // !defined(CYG_HAL_STARTUP_RAM)
#if defined(CYG_HAL_STARTUP_ROM)
// Relocate data from ROM to RAM
{
register cyg_uint32 *p, *q;
for( p = &__ram_data_start, q = &__rom_data_start;
p < &__ram_data_end;
p++, q++ )
*p = *q;
}
/*
// Relocate data from ROM to SRAM
{
register cyg_uint32 *p, *q;
for( p = &__sram_data_start, q = &__srom_data_start;
p < &__sram_data_end;
p++, q++ )
*p = *q;
}
*/
#endif
// Clear BSS
{
register cyg_uint32 *p;
for( p = &__bss_start; p < &__bss_end; p++ )
*p = 0;
}
// Initialize interrupt vectors. Set the levels for all interrupts
// to default values. Also set the default priorities of the
// system handlers: all exceptions maximum priority except SVC and
// PendSVC which are lowest priority.
{
register int i;
HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR0, 0x00000000 );
HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR1, 0xFF000000 );
HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, 0x00FF0000 );
hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SYS_TICK] = (CYG_ADDRESS)hal_default_isr;
for( i = 1; i < CYGNUM_HAL_ISR_COUNT; i++ )
{
hal_interrupt_handlers[i] = (CYG_ADDRESS)hal_default_isr;
HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(i-CYGNUM_HAL_INTERRUPT_EXTERNAL), 0x80 );
}
}
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
// Enable DebugMonitor exceptions. This is needed to enable single
// step. This only has an effect if no external JTAG device is
// attached.
{
CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE;
cyg_uint32 demcr;
HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
demcr |= CYGARC_REG_DEBUG_DEMCR_MON_EN;
HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
}
#endif
#if !defined(CYG_HAL_STARTUP_RAM)
// Enable Usage, Bus and Mem fault handlers. Do this for ROM and
// JTAG startups. For RAM startups, this will have already been
// done by the ROM monitor.
{
CYG_ADDRESS base = CYGARC_REG_NVIC_BASE;
cyg_uint32 shcsr;
HAL_READ_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
shcsr |= CYGARC_REG_NVIC_SHCSR_USGFAULTENA;
shcsr |= CYGARC_REG_NVIC_SHCSR_BUSFAULTENA;
shcsr |= CYGARC_REG_NVIC_SHCSR_MEMFAULTENA;
HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
}
#endif
// Call variant and platform init routines
hal_variant_init();
hal_platform_init();
// Start up the system clock
HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
initialize_stub();
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \
defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
hal_ctrlc_isr_init();
#endif
// Run through static constructors
cyg_hal_invoke_constructors();
// Finally call into application
cyg_start();
for(;;);
}
