uint32_t Ethernet_Init()
{
	ETH_InitTypeDef init;
	ETH_DMADescTypeDef  DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB]; //Rx & Tx DMA Descriptors
	uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE]; // Receive buffers
	uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE]; // Transmit buffers

	uint8_t mac[6] = {0x12,0x34,0x13,0x14,0x00,0x10};

	init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;  // ETH_AUTONEGOTIATION_DISABLE
	init.Speed = ETH_SPEED_100M;							// ETH_SPEED_10M
	init.DuplexMode = ETH_MODE_FULLDUPLEX; 				// ETH_MODE_HALFDUPLEX
	init.PhyAddress = 0x0; //This parameter must be a number between Min_Data = 0 and Max_Data = 32
	init.MACAddr = mac; //MAC Address of used Hardware: must be pointer on an array of 6 bytes
	init.RxMode = ETH_RXPOLLING_MODE; 					//ETH_RXINTERRUPT_MODE
	init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE; 		// ETH_CHECKSUM_BY_HARDWARE
	init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;		// ETH_MEDIA_INTERFACE_RMII

	heth.Init = init;

	HAL_ETH_Init(&heth);

	init_CLock();
	init_PortA();
	init_PortB();
	init_PortC();

	HAL_ETH_DMATxDescListInit(&heth, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
	HAL_ETH_DMARxDescListInit(&heth, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);

	return 1;
}
/**
  * @brief In this function, the hardware should be initialized.
  * Called from ethernetif_init().
  *
  * @param netif the already initialized lwip network interface structure
  *        for this ethernetif
  */
static void low_level_init(struct netif *netif)
{
  uint8_t macaddress[6]= { MAC_ADDR0, MAC_ADDR1, MAC_ADDR2, MAC_ADDR3, MAC_ADDR4, MAC_ADDR5 };
  
  EthHandle.Instance = ETH;  
  EthHandle.Init.MACAddr = macaddress;
  EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
  EthHandle.Init.Speed = ETH_SPEED_100M;
  EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
  EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
  EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
  EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
  EthHandle.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
  
  /* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
  if (HAL_ETH_Init(&EthHandle) == HAL_OK)
  {
    /* Set netif link flag */
    netif->flags |= NETIF_FLAG_LINK_UP;
  }
  
  /* Initialize Tx Descriptors list: Chain Mode */
  HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
     
  /* Initialize Rx Descriptors list: Chain Mode  */
  HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
  
  /* set netif MAC hardware address length */
  netif->hwaddr_len = ETHARP_HWADDR_LEN;

  /* set netif MAC hardware address */
  netif->hwaddr[0] =  MAC_ADDR0;
  netif->hwaddr[1] =  MAC_ADDR1;
  netif->hwaddr[2] =  MAC_ADDR2;
  netif->hwaddr[3] =  MAC_ADDR3;
  netif->hwaddr[4] =  MAC_ADDR4;
  netif->hwaddr[5] =  MAC_ADDR5;

  /* set netif maximum transfer unit */
  netif->mtu = 1500;

  /* Accept broadcast address and ARP traffic */
  netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;

  /* create a binary semaphore used for informing ethernetif of frame reception */
  osSemaphoreDef(SEM);
  s_xSemaphore = osSemaphoreCreate(osSemaphore(SEM) , 1 );

  /* create the task that handles the ETH_MAC */
  osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE);
  osThreadCreate (osThread(EthIf), netif);

  /* Enable MAC and DMA transmission and reception */
  HAL_ETH_Start(&EthHandle);
}
Exemple #3
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/* ETH init function */
void MX_ETH_Init(void)
{

   uint8_t MACAddr[6] ;

  heth.Instance = ETH;
  heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
  heth.Init.PhyAddress = 1;
  MACAddr[0] = 0x00;
  MACAddr[1] = 0x80;
  MACAddr[2] = 0xE1;
  MACAddr[3] = 0x00;
  MACAddr[4] = 0x00;
  MACAddr[5] = 0x00;
  heth.Init.MACAddr = &MACAddr[0];
  heth.Init.RxMode = ETH_RXPOLLING_MODE;
  heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
  heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
  HAL_ETH_Init(&heth);

}
static void low_level_init(struct netif *netif)
{
  uint8_t macaddress[6];
  uint32_t regvalue = 0;

  // Get Ethernet MAC address
  stm32f_set_mac_addr((uint8_t*) macaddress);

  EthHandle.Instance = ETH;
  EthHandle.Init.MACAddr = macaddress;
  EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
  EthHandle.Init.Speed = ETH_SPEED_100M;
  EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
  EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII;
  EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
  EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
  EthHandle.Init.PhyAddress = DP83848_PHY_ADDRESS;

  /* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
  if (HAL_ETH_Init(&EthHandle) == HAL_OK)
  {
    /* Set netif link flag */
    netif->flags |= NETIF_FLAG_LINK_UP;
  }

  /* Initialize Tx Descriptors list: Chain Mode */
  HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);

  /* Initialize Rx Descriptors list: Chain Mode  */
  HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);

  /* set MAC hardware address length */
  netif->hwaddr_len = ETHARP_HWADDR_LEN;

  /* set netif MAC hardware address */
  stm32f_set_mac_addr((uint8_t*) netif->hwaddr);

  /* maximum transfer unit */
  netif->mtu = 1500;

  /* device capabilities */
  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
  netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;

  /* Enable MAC and DMA transmission and reception */
  HAL_ETH_Start(&EthHandle);

  /**** Configure PHY to generate an interrupt when Eth Link state changes ****/
  /* Read Register Configuration */
  HAL_ETH_ReadPHYRegister(&EthHandle, PHY_MICR, &regvalue);

  regvalue |= (PHY_MICR_INT_EN | PHY_MICR_INT_OE);

  /* Enable Interrupts */
  HAL_ETH_WritePHYRegister(&EthHandle, PHY_MICR, regvalue );

  /* Read Register Configuration */
  HAL_ETH_ReadPHYRegister(&EthHandle, PHY_MISR, &regvalue);

  regvalue |= PHY_MISR_LINK_INT_EN;

  /* create a binary semaphore used for informing ethernetif of frame reception */
  osSemaphoreDef( SEM , rtems_build_name( 'E', 'T', 'H', 'I' ));
  s_xSemaphore = osSemaphoreCreate( osSemaphore( SEM ), 0 );

  /* create the task that handles the ETH_MAC */
  osThreadDef( EthIf,
    ethernetif_input,
    osPriorityRealtime,
    1,
    INTERFACE_THREAD_STACK_SIZE,
    rtems_build_name( 'E', 'T', 'H', 'I' ));

  osThreadCreate( osThread( EthIf ), netif );

  /* Enable Interrupt on change of link status */
  HAL_ETH_WritePHYRegister(&EthHandle, PHY_MISR, regvalue);
}
Exemple #5
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status_t eth_init(const uint8_t *mac_addr, eth_phy_itf eth_phy)
{
    LTRACE_ENTRY;

    DEBUG_ASSERT(mac_addr);

    eth.eth_phy = eth_phy;

    /* Enable ETHERNET clock  */
    __HAL_RCC_ETH_CLK_ENABLE();

    eth.EthHandle.Instance = ETH;
    eth.EthHandle.Init.MACAddr = (uint8_t *)mac_addr;
    eth.EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
    eth.EthHandle.Init.Speed = ETH_SPEED_100M;
    eth.EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
    switch (eth_phy) {
        case PHY_DP83848:
            eth.EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII;
            eth.EthHandle.Init.PhyAddress = DP83848_PHY_ADDRESS;
            break;
        case PHY_LAN8742A:
            eth.EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
            eth.EthHandle.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
            break;
        case PHY_KSZ8721:
            eth.EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
            eth.EthHandle.Init.PhyAddress = KSZ8721_PHY_ADDRESS;
            break;
        default:
            return ERR_NOT_CONFIGURED;
    }

    eth.EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
    //eth.EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; // XXX icmp checksums corrupted if stack stuff valid checksum
    eth.EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;

    /* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
    if (HAL_ETH_Init(&eth.EthHandle) != HAL_OK)
        return ERR_NOT_CONFIGURED;

    /* allocate descriptor and buffer memory from DTCM */
    /* XXX do in a more generic way */
#if MEMBASE == 0x20000000
#error DTCM will collide with MEMBASE
#endif
    addr_t tcm_ptr = RAMDTCM_BASE;

    eth.DMATxDscrTab = (void *)tcm_ptr;
    tcm_ptr += sizeof(*eth.DMATxDscrTab) * ETH_TXBUFNB;
    eth.DMARxDscrTab = (void *)tcm_ptr;
    tcm_ptr += sizeof(*eth.DMARxDscrTab) * ETH_RXBUFNB;

    eth.Tx_Buff = (void *)tcm_ptr;
    tcm_ptr += ETH_TX_BUF_SIZE * ETH_TXBUFNB;
    eth.Rx_Buff = (void *)tcm_ptr;
    tcm_ptr += ETH_RX_BUF_SIZE * ETH_RXBUFNB;

    /* Initialize Tx Descriptors list: Chain Mode */
    HAL_ETH_DMATxDescListInit(&eth.EthHandle, eth.DMATxDscrTab, eth.Tx_Buff, ETH_TXBUFNB);

    /* Initialize Rx Descriptors list: Chain Mode  */
    HAL_ETH_DMARxDescListInit(&eth.EthHandle, eth.DMARxDscrTab, eth.Rx_Buff, ETH_RXBUFNB);

    /* Enable MAC and DMA transmission and reception */
    HAL_ETH_Start(&eth.EthHandle);

#if 0
    // XXX DP83848 specific
    /**** Configure PHY to generate an interrupt when Eth Link state changes ****/
    /* Read Register Configuration */
    uint32_t regvalue;
    HAL_ETH_ReadPHYRegister(&eth.EthHandle, PHY_MICR, &regvalue);

    regvalue |= (PHY_MICR_INT_EN | PHY_MICR_INT_OE);

    /* Enable Interrupts */
    HAL_ETH_WritePHYRegister(&eth.EthHandle, PHY_MICR, regvalue );

    /* Read Register Configuration */
    HAL_ETH_ReadPHYRegister(&eth.EthHandle, PHY_MISR, &regvalue);

    regvalue |= PHY_MISR_LINK_INT_EN;

    /* Enable Interrupt on change of link status */
    HAL_ETH_WritePHYRegister(&eth.EthHandle, PHY_MISR, regvalue);
#endif

    /* set up an event to block the rx thread on */
    event_init(&eth.rx_event, false, EVENT_FLAG_AUTOUNSIGNAL);

    /* start worker thread */
    thread_resume(thread_create("eth_rx", &eth_rx_worker, NULL, HIGH_PRIORITY, DEFAULT_STACK_SIZE));

    /* enable interrupts */
    HAL_NVIC_EnableIRQ(ETH_IRQn);

    LTRACE_EXIT;

    return NO_ERROR;
}
BaseType_t xNetworkInterfaceInitialise(void) {

	HAL_StatusTypeDef hal_eth_init_status;
	uint8_t status = 0;

	/* Init ETH */

	heth_global.Instance = ETH;
	heth_global.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
	heth_global.Init.Speed = ETH_SPEED_100M;
	heth_global.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
	heth_global.Init.PhyAddress = DP83848_PHY_ADDRESS;

	heth_global.Init.MACAddr = &ucMACAddress[0];
	heth_global.Init.RxMode = ETH_RXINTERRUPT_MODE;
#if (ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM == 1) && (ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM == 1)
	heth_global.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
#else
	heth_global.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
#endif

	heth_global.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;

	hal_eth_init_status = HAL_ETH_Init(&heth_global);

	if (hal_eth_init_status == HAL_OK) {
		print_console(">> MAC init OK\r\n");
		status = pdPASS;
	}
	else {
		return pdFAIL;
		print_console(">> MAC init failed\r\n");
	}

	probePHY(&heth_global);

	/* Initialize Tx Descriptors list: Chain Mode */
	HAL_ETH_DMATxDescListInit(&heth_global, DMATxDscrTab, &Tx_Buff[0][0],
	ETH_TXBUFNB);
	//HAL_ETH_DMATxDescListInit(&heth_global, DMATxDscrTab, NULL, ETH_TXBUFNB);

	//InitializeZeroCopyBuffersTx(ETH_TXBUFNB,DMATxDscrTab);

	/* Initialize zero copy buffers */
	//uint8_t* zerocopy_bufor_tab[ETH_RXBUFNB]; //  tab to hold pointers to zero copy bufors
	/* Initialize Rx Descriptors list: Chain Mode  */
	HAL_ETH_DMARxDescListInit(&heth_global, DMARxDscrTab, &Rx_Buff[0][0],
	ETH_RXBUFNB);

	/* Enable MAC and DMA transmission and reception */
	HAL_ETH_Start(&heth_global);

	setPHYleds(&heth_global);

#if PHY_LINK_CHANGE_INT

	uint32_t regvalue = 0;

	/**** Configure PHY to generate an interrupt when Eth Link state changes ****/
	/* Read Register Configuration */
	HAL_ETH_ReadPHYRegister(&heth_global, PHY_MICR, &regvalue);

	regvalue |= (PHY_MICR_INT_EN | PHY_MICR_INT_OE);

	/* Enable Interrupts */
	HAL_ETH_WritePHYRegister(&heth_global, PHY_MICR, regvalue );

	/* Read Register Configuration */
	HAL_ETH_ReadPHYRegister(&heth_global, PHY_MISR, &regvalue);

	regvalue |= PHY_MISR_LINK_INT_EN;

	/* Enable Interrupt on change of link status */
	HAL_ETH_WritePHYRegister(&heth_global, PHY_MISR, regvalue);

#endif

	xTaskCreate(prvEMACDeferredInterruptHandlerTask, "EthRcvTask", configMINIMAL_STACK_SIZE, NULL,
			configMAX_PRIORITIES-1, NULL);

	return status;

}