/* * @brief */ static void SPI_SetClkDiv(SPI_T *spi, uint16_t div) { uint8_t n = 0; if (div < 1) { return; } if (div > 2 * (0xFF + 1)) { HAL_CLR_BIT(spi->CCTR, SPI_CCTR_DRS_MASK); do { div = (div == 1) ? 0 : ((div + 1) / 2); n++; } while (div); HAL_MODIFY_REG(spi->CCTR, SPI_CCTR_CDR1_MASK, (n & 0x0F) << SPI_CCTR_CDR1_SHIFT); } else { HAL_SET_BIT(spi->CCTR, SPI_CCTR_DRS_MASK); n = ((div + 1) / 2) - 1; HAL_MODIFY_REG(spi->CCTR, SPI_CCTR_CDR2_MASK, (n & 0xFF) << SPI_CCTR_CDR2_SHIFT); } }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_AutoChipSelect(SPI_T *spi, SPI_TCTRL_SS_Sel cs, bool cs_remain) { HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_SEL_MASK, cs); HAL_CLR_BIT(spi->TCTRL, SPI_TCTRL_SS_OWNER_MASK); HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_CTL_MASK, (!cs_remain) << SPI_TCTRL_SS_CTL_SHIFT); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetDataSize(SPI_T *spi, rt_uint32_t data_size, rt_uint32_t dummy_size) { HAL_MODIFY_REG(spi->BC, SPI_BC_MBC_MASK, data_size + dummy_size); HAL_MODIFY_REG(spi->TC, SPI_TC_MWTC_MASK, data_size); HAL_MODIFY_REG(spi->BCC, SPI_BCC_STC_MASK, data_size); }
HAL_Status Hal_FlashCache_Init(FlashCache_Config *cfg) { // uint32_t cache_line = (cfg->cache_size * 8 + 127) / 128; // uint32_t cache_line = (CACHE_SIZE * 8 + 127) / 128; /* check param */ if (/*(cache_line > 0x1FF) || */(cfg->addr_bias & (~FLASH_CACHE_READ_BIAS_ADDR_MASK))) { return HAL_INVALID; } /* CCMU Enable */ // HAL_MODIFY_REG(FLASH_CACHE, FLASH_CACHE_COM_CTRL_SIZE_MASK, cache_line << FLASH_CACHE_COM_CTRL_SIZE_SHIFT); HAL_MODIFY_REG(FLASH_CACHE->MIN_ADDR, FLASH_CACHE_MIN_ADDR_MASK, CACHE_START_ADDR << FLASH_CACHE_MIN_ADDR_SHIFT); HAL_MODIFY_REG(FLASH_CACHE->MAX_ADDR, FLASH_CACHE_MAX_ADDR_MASK, CACHE_END_ADDR << FLASH_CACHE_MAX_ADDR_SHIFT); HAL_MODIFY_REG(FLASH_CACHE->READ_BIAS_ADDR, FLASH_CACHE_READ_BIAS_ADDR_MASK, cfg->addr_bias << FLASH_CACHE_READ_BIAS_ADDR_SHIFT); FC_REG_ALL(); return HAL_OK; }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_DMA(SPI_T *spi, bool txEn, bool rxEn) { HAL_MODIFY_REG(spi->FCTL, SPI_FCTL_TF_DRQ_EN_MASK | SPI_FCTL_RF_DRQ_EN_MASK, ((!!txEn) << SPI_FCTL_TF_DRQ_EN_SHIFT) | ((!!rxEn) << SPI_FCTL_RF_DRQ_EN_SHIFT)); }
HAL_Status Hal_FlashCache_DisablePrefetch() { HAL_MODIFY_REG(FLASH_CACHE->PREFETCH_CTRL, FLASH_CACHE_PREFETCH_CTRL_STOP_MASK, (FLASH_CACHE_PREFETCH_DISABLE << FLASH_CACHE_PREFETCH_CTRL_STOP_SHIFT)); return HAL_OK; }
/** * @brief Initialize the specified GPIO * @param[in] port GPIO port * @param[in] pin GPIO pin number * @param[in] param Pointer to GPIO_InitParam structure * @return None */ void HAL_GPIO_Init(GPIO_Port port, GPIO_Pin pin, const GPIO_InitParam *param) { uint32_t regIdx; uint32_t bitShift; GPIO_CTRL_T *gpiox; unsigned long flags; #if 0 HAL_ASSERT_PARAM(pin <= GPIO_PIN_MAX); HAL_ASSERT_PARAM(param->mode <= GPIO_CTRL_MODE_MAX); HAL_ASSERT_PARAM(param->driving <= GPIO_CTRL_DRIVING_MAX); HAL_ASSERT_PARAM(param->pull <= GPIO_CTRL_PULL_MAX); #endif flags = HAL_EnterCriticalSection(); if (gGPIOUsedCnt++ == 0) { HAL_CCM_BusEnablePeriphClock(CCM_BUS_PERIPH_BIT_GPIO); #ifdef CONFIG_PM if (!hal_gpio_suspending) { pm_register_ops(GPIO_DEV); } #endif } gpiox = GPIO_GetCtrlInstance(port); /* set working mode (function) */ GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_MODE_BITS); HAL_MODIFY_REG(gpiox->MODE[regIdx], GPIO_CTRL_MODE_VMASK << bitShift, (param->mode & GPIO_CTRL_MODE_VMASK) << bitShift); /* set driving */ GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_DRIVING_BITS); HAL_MODIFY_REG(gpiox->DRIVING[regIdx], GPIO_CTRL_DRIVING_VMASK << bitShift, (param->driving & GPIO_CTRL_DRIVING_VMASK) << bitShift); /* set pull */ GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_PULL_BITS); HAL_MODIFY_REG(gpiox->PULL[regIdx], GPIO_CTRL_PULL_VMASK << bitShift, (param->pull & GPIO_CTRL_PULL_VMASK) << bitShift); HAL_ExitCriticalSection(flags); }
/* * Clock */ void HAL_PRCM_SetLFCLKSource(PRCM_LFCLKSrc src) { /* always enable inter 32K for external 32K is not ready at startup */ uint32_t clr_mask = PRCM_LFCLK_SRC_MASK | PRCM_LFCLK_EXT32K_EN_BIT; uint32_t set_mask = src | PRCM_LFCLK_INTER32K_EN_BIT; if (src == PRCM_LFCLK_SRC_EXT32K) { set_mask |= PRCM_LFCLK_EXT32K_EN_BIT; } HAL_MODIFY_REG(PRCM->SYS_LFCLK_CTRL, clr_mask, set_mask); }
HAL_Status Hal_FlashCache_EnablePrefetch(FlashCache_PrefetchConfig *cfg) { /* uint32_t cache_line = (cfg->prefetch_cache_size * 8 + 127) / 128; if (cache_line >= CACHE_LINE_MAX) return HAL_INVALID; */ HAL_MODIFY_REG(FLASH_CACHE->PREFETCH_START_ADDR, FLASH_CACHE_PREFETCH_START_ADDR_MASK, cfg->addr_prefetch_start << FLASH_CACHE_PREFETCH_START_ADDR_SHIFT); HAL_MODIFY_REG(FLASH_CACHE->PREFETCH_CTRL, // FLASH_CACHE_PREFETCH_CTRL_SIZE_MASK | FLASH_CACHE_PREFETCH_CTRL_BRANCH_MASK | FLASH_CACHE_PREFETCH_CTRL_STOP_MASK, // (cache_line << FLASH_CACHE_PREFETCH_CTRL_SIZE_SHIFT) | (cfg->prefetch_2nd_branch << FLASH_CACHE_PREFETCH_CTRL_BRANCH_SHIFT) | (FLASH_CACHE_PREFETCH_ENABLE << FLASH_CACHE_PREFETCH_CTRL_STOP_SHIFT)); return HAL_OK; }
void HAL_PRCM_SetCPUAClk(PRCM_CPUClkSrc src, PRCM_SysClkFactor factor) { switch (src) { case PRCM_CPU_CLK_SRC_HFCLK: HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_CPU_CLK_SRC_MASK, PRCM_CPU_CLK_SRC_HFCLK); break; case PRCM_CPU_CLK_SRC_LFCLK: HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_CPU_CLK_SRC_MASK, PRCM_CPU_CLK_SRC_LFCLK); break; case PRCM_CPU_CLK_SRC_SYSCLK: default: #if 1 HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_SYS_CLK_FACTOR_MASK, factor); HAL_SET_BIT(PRCM->SYS_CLK1_CTRL, PRCM_SYS_CLK_EN_BIT); HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_CPU_CLK_SRC_MASK, PRCM_CPU_CLK_SRC_SYSCLK); #else PRCM->SYS_CLK1_CTRL = PRCM_SYS_CLK_EN_BIT | factor | PRCM_CPU_CLK_SRC_SYSCLK; #endif break; } }
/** * @brief Deinitialize the specified GPIO * @param[in] port GPIO port * @param[in] pin GPIO pin number * @return None * @note After deinitialization, the GPIO is in its reset state: * (GPIOx_Pn_F7_DISABLE, GPIO_DRIVING_LEVEL_1, GPIO_PULL_NONE). */ void HAL_GPIO_DeInit(GPIO_Port port, GPIO_Pin pin) { uint32_t regIdx; uint32_t bitShift; GPIO_CTRL_T *gpiox; unsigned long flags; flags = HAL_EnterCriticalSection(); gpiox = GPIO_GetCtrlInstance(port); /* set working mode (function) to disable */ GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_MODE_BITS); HAL_MODIFY_REG(gpiox->MODE[regIdx], GPIO_CTRL_MODE_VMASK << bitShift, (GPIOx_Pn_F7_DISABLE & GPIO_CTRL_MODE_VMASK) << bitShift); /* set driving to default value (GPIO_DRIVING_LEVEL_1) */ GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_DRIVING_BITS); HAL_MODIFY_REG(gpiox->DRIVING[regIdx], GPIO_CTRL_DRIVING_VMASK << bitShift, (GPIO_DRIVING_LEVEL_1 & GPIO_CTRL_DRIVING_VMASK) << bitShift); /* set pull to default value (GPIO_PULL_NONE) */ GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_CTRL_PULL_BITS); HAL_MODIFY_REG(gpiox->PULL[regIdx], GPIO_CTRL_PULL_VMASK << bitShift, (GPIO_PULL_NONE & GPIO_CTRL_PULL_VMASK) << bitShift); if ((gGPIOUsedCnt > 0) && (--gGPIOUsedCnt == 0)) { HAL_CCM_BusDisablePeriphClock(CCM_BUS_PERIPH_BIT_GPIO); #ifdef CONFIG_PM if (!hal_gpio_suspending) { pm_unregister_ops(GPIO_DEV); } #endif } HAL_ExitCriticalSection(flags); }
/** * @brief Enable the IRQ of the specified GPIO * @param[in] port GPIO port * @param[in] pin GPIO pin number * @param[in] param Pointer to GPIO_IrqParam structure * @return None */ void HAL_GPIO_EnableIRQ(GPIO_Port port, GPIO_Pin pin, const GPIO_IrqParam *param) { uint32_t regIdx; uint32_t bitShift; GPIO_IRQ_T *gpiox; GPIO_Private *gpioPriv; IRQn_Type IRQn; unsigned long flags; flags = HAL_EnterCriticalSection(); if (port == GPIO_PORT_A) { gpioPriv = gGPIOAPrivate; IRQn = GPIOA_IRQn; } else if (port == GPIO_PORT_B) { gpioPriv = gGPIOBPrivate; IRQn = GPIOB_IRQn; } else { HAL_ERR("Invalid port %d for IRQ\n", port); return; } gpiox = GPIO_GetIRQInstance(port); /* set callback */ gpioPriv[pin].callback = param->callback; gpioPriv[pin].arg = param->arg; /* set IRQ trigger mode */ GPIO_GET_REG_IDX_SHIFT(regIdx, bitShift, pin, GPIO_IRQ_EVT_BITS); HAL_MODIFY_REG(gpiox->IRQ_MODE[regIdx], GPIO_IRQ_EVT_VMASK << bitShift, (param->event & GPIO_IRQ_EVT_VMASK) << bitShift); if (GPIO_IsPendingIRQ(gpiox, pin)) { GPIO_ClearPendingIRQ(gpiox, pin); } GPIO_EnableIRQ(gpiox, pin); HAL_NVIC_SetPriority(IRQn, NVIC_PERIPHERAL_PRIORITY_DEFAULT); HAL_NVIC_EnableIRQ(IRQn); HAL_ExitCriticalSection(flags); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetRxFifoThreshold(SPI_T *spi, uint8_t threshold) { HAL_MODIFY_REG(spi->FCTL, SPI_FCTL_RX_TRIG_LEVEL_MASK, threshold << SPI_FCTL_RX_TRIG_LEVEL_SHIFT); }
void HAL_PRCM_SetLDO1Voltage(PRCM_LDO1Volt volt) { HAL_MODIFY_REG(PRCM->SYS_LDO_SW_CTRL, PRCM_LDO1_VOLT_MASK, volt); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetSclkMode(SPI_T *spi, SPI_SCLK_Mode mode) { HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_CPOL_MASK | SPI_TCTRL_CPHA_MASK, mode); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetCsIdle(SPI_T *spi, bool idle) { HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SPOL_MASK, (!!idle) << SPI_TCTRL_SPOL_SHIFT); }
__STATIC_INLINE void ADC_SetFirstDelay(uint32_t firstDelay) { HAL_MODIFY_REG(ADC->CTRL, ADC_FIRST_DELAY_MASK, HAL_GET_BIT(firstDelay << ADC_FIRST_DELAY_SHIFT, ADC_FIRST_DELAY_MASK)); }
__STATIC_INLINE void ADC_SetLowValue(ADC_Channel chan, uint32_t value) { HAL_MODIFY_REG(ADC->CMP_DATA[chan], ADC_LOW_DATA_MASK, HAL_GET_BIT(value << ADC_LOW_DATA_SHIFT, ADC_LOW_DATA_MASK)); }
void HAL_PRCM_DisCLK1(PRCM_SysClkFactor factor) { HAL_MODIFY_REG(PRCM->SYS_CLK1_CTRL, PRCM_SYS_CLK_FACTOR_MASK, factor); HAL_CLR_BIT(PRCM->SYS_CLK1_CTRL, PRCM_SYS_CLK_EN_BIT); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetDuplex(SPI_T *spi, SPI_TCTRL_DHB_Duplex duplex) { HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_DHB_MASK, duplex); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_EnableRapidsMode(SPI_T *spi, bool delay_sample) { HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_RPSM_MASK); HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SDC_MASK, delay_sample << SPI_TCTRL_SDC_SHIFT); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetFirstTransmitBit(SPI_T *spi, SPI_TCTRL_Fbs bit) { HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_FBS_MASK, bit); }
__STATIC_INLINE void ADC_SetOPBias(uint32_t opBias) { HAL_MODIFY_REG(ADC->CTRL, ADC_OP_BIAS_MASK, HAL_GET_BIT(opBias << ADC_OP_BIAS_SHIFT, ADC_OP_BIAS_MASK)); }
__STATIC_INLINE void ADC_SetWorkMode(ADC_WorkMode workMode) { HAL_MODIFY_REG(ADC->CTRL, ADC_WORK_MODE_MASK, HAL_GET_BIT(workMode << ADC_WORK_MODE_SHIFT, ADC_WORK_MODE_MASK)); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetInterval(SPI_T *spi, uint16_t nSCLK) { HAL_MODIFY_REG(spi->WAIT, SPI_WAIT_WCC_MASK, nSCLK << SPI_WAIT_WCC_SHIFT); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetCsLevel(SPI_T *spi, bool level) { HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_LEVEL_MASK, level << SPI_TCTRL_SS_LEVEL_SHIFT); }
/* * Power * - DCDC * - Power switch * - LDO */ void HAL_PRCM_SetDCDCVoltage(PRCM_DCDCVolt volt) { HAL_MODIFY_REG(PRCM->SYS_DCDC_CTRL, PRCM_DCDC_VOLT_MASK, volt); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_ManualChipSelect(SPI_T *spi, SPI_TCTRL_SS_Sel cs) { HAL_SET_BIT(spi->TCTRL, SPI_TCTRL_SS_OWNER_MASK); HAL_MODIFY_REG(spi->TCTRL, SPI_TCTRL_SS_SEL_MASK, cs); }
/* * @brief */ __SPI_STATIC_INLINE__ void SPI_SetMode(SPI_T *spi, SPI_CTRL_Mode mode) { HAL_MODIFY_REG(spi->CTRL, SPI_CTRL_MODE_MASK, mode); }
__STATIC_INLINE void ADC_SetFifoLevel(uint8_t level) { HAL_MODIFY_REG(ADC->FIFO_CTRL, ADC_FIFO_LEVEL_MASK, HAL_GET_BIT((level - 1) << ADC_FIFO_LEVEL_SHIFT, ADC_FIFO_LEVEL_MASK)); }