externC void hal_ppc405_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid) { cyg_uint8 req; cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn); if ((dev >= CYG_PCI_MIN_DEV) && (dev < CYG_PCI_MAX_DEV)) { HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req); if (0 != req) { #ifdef CYG_PCI_IRQ_MAP char pci_irq_table[][4] = CYG_PCI_IRQ_MAP; #else #error "Need platform defined IRQ map" #endif *vec = pci_irq_table[dev-CYG_PCI_MIN_DEV][req-1]; *valid = (*vec != -1); } else { /* Device will not generate interrupt requests. */ *valid = false; } #if defined(CYGPKG_IO_PCI_DEBUG) diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec); #endif } else { *valid = false; // Invalid device } }
void cyg_hal_plf_pci_translate_interrupt(cyg_uint32 bus, cyg_uint32 devfn, CYG_ADDRWORD *vec, cyg_bool *valid) { cyg_uint8 pin; cyg_uint32 slot = 3 - (CYG_PCI_DEV_GET_DEV(devfn) - 18); HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, pin); *vec = -1; *valid = false; if (slot < IXP425_PCI_MAX_DEV && pin <= IXP425_PCI_IRQ_LINES) { *vec = pci_irq_table[slot][pin-1]; *valid = true; } }
externC void _mb93091_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid) { cyg_uint8 req; cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn); if (dev == CYG_PCI_MIN_DEV) { // On board LAN *vec = CYGNUM_HAL_INTERRUPT_LAN; *valid = true; } else { HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req); if (0 != req) { CYG_ADDRWORD __translation[4] = { CYGNUM_HAL_INTERRUPT_PCIINTC, /* INTC# */ CYGNUM_HAL_INTERRUPT_PCIINTB, /* INTB# */ CYGNUM_HAL_INTERRUPT_PCIINTA, /* INTA# */ CYGNUM_HAL_INTERRUPT_PCIINTD}; /* INTD# */ /* The PCI lines from the different slots are wired like this */ /* on the PCI backplane: */ /* pin6A pin7B pin7A pin8B */ /* I/O Slot 1 INTA# INTB# INTC# INTD# */ /* I/O Slot 2 INTD# INTA# INTB# INTC# */ /* I/O Slot 3 INTC# INTD# INTA# INTB# */ /* */ /* (From PCI Development Backplane, 3.2.2 Interrupts) */ /* */ /* Devsel signals are wired to, resulting in device IDs: */ /* I/O Slot 1 AD30 / dev 19 [(8+1)&3 = 1] */ /* I/O Slot 2 AD29 / dev 18 [(7+1)&3 = 0] */ /* I/O Slot 3 AD28 / dev 17 [(6+1)&3 = 3] */ *vec = __translation[((req+dev)&3)]; *valid = true; } else { /* Device will not generate interrupt requests. */ *valid = false; } diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec); } }
externC void hal_ppc405_pci_init(void) { static int _init = 0; cyg_uint8 next_bus; cyg_uint32 cmd_state, bridge_state; if (_init) return; _init = 1; // Configure PCI bridge HAL_WRITE_UINT32LE(PCIL0_PMM0PCILA, 0); HAL_WRITE_UINT32LE(PCIL0_PMM0PCIHA, 0); HAL_WRITE_UINT32LE(PCIL0_PMM0LA, HAL_PCI_PHYSICAL_MEMORY_BASE); HAL_WRITE_UINT32LE(PCIL0_PMM0MA, ~(0x10000000-1) | 0x00000001); HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0); HAL_WRITE_UINT32LE(PCIL0_PTM1LA, 0); HAL_WRITE_UINT32LE(PCIL0_PTM1MS, ~(0x10000000-1) | 0x00000001); // Indicate that the bridge has been configured HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state); bridge_state |= 0x0001; HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state); // Setup for bus mastering HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, cmd_state); cyg_pci_init(); if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) { #if defined(CYGPKG_IO_PCI_DEBUG) diag_printf("Configure PCI bus\n"); #endif HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_PARITY | CYG_PCI_CFG_COMMAND_SERR); // Setup latency timer field HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_LATENCY_TIMER, 32); // Configure PCI bus. next_bus = 1; cyg_pci_configure_bus(0, &next_bus); } #if defined(CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS) if (1) { cyg_uint8 req; cyg_uint8 devfn; cyg_pci_device_id devid; cyg_pci_device dev_info; int i; devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN; while (cyg_pci_find_next(devid, &devid)) { devfn = CYG_PCI_DEV_GET_DEVFN(devid); cyg_pci_get_device_info(devid, &dev_info); HAL_PCI_CFG_READ_UINT8(0, devfn, CYG_PCI_CFG_INT_PIN, req); diag_printf("\n"); diag_printf("Bus: %d", CYG_PCI_DEV_GET_BUS(devid)); diag_printf(", PCI Device: %d", CYG_PCI_DEV_GET_DEV(devfn)); diag_printf(", PCI Func: %d\n", CYG_PCI_DEV_GET_FN(devfn)); diag_printf(" Vendor Id: 0x%04X", dev_info.vendor); diag_printf(", Device Id: 0x%04X", dev_info.device); diag_printf(", Command: 0x%04X", dev_info.command); diag_printf(", IRQ: %d\n", req); for (i = 0; i < dev_info.num_bars; i++) { diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]); diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n", dev_info.base_size[i], dev_info.base_map[i]); } } } #endif }
// Read functions void cyg_pcihw_read_config_uint8( cyg_uint8 bus, cyg_uint8 devfn, cyg_uint8 offset, cyg_uint8 *val) { HAL_PCI_CFG_READ_UINT8(bus, devfn, offset, *val); }