externC void
cyg_var_enable_caches(void)
{
// If relying on a ROM monitor do not invalidate the caches as the
// ROM monitor may have (non-synced) state in the caches.
#if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
// Initialize cache.
HAL_UCACHE_INVALIDATE_ALL();
// Set cache modes
HAL_UCACHE_WRITE_MODE_SH(CACHE_MODE_P0|CACHE_MODE_P1);
#endif
#ifdef CYGHWR_HAL_SH_CACHE_ENABLE
// Enable cache.
HAL_UCACHE_ENABLE();
#endif
}
// -------------------------------------------------------------------------
// Hardware init
void hal_hardware_init(void)
{
cyg_uint32 intmask;
// Set up eCos/ROM interfaces
hal_if_init();
// Enable cache
HAL_WRITE_UINT32(E7T_SYSCFG,
0x07FFFF80|E7T_SYSCFG_CM_0R_8C|E7T_SYSCFG_WE);
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
// Clear global interrupt mask bit
HAL_READ_UINT32(E7T_INTMSK, intmask);
intmask &= ~E7T_INTMSK_GLOBAL;
HAL_WRITE_UINT32(E7T_INTMSK, intmask);
}
void hal_hardware_init(void)
{
// Any hardware/platform initialization that needs to be done.
// Set all unknowns as edge triggered
HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR0,
ICTL_ICR0_CH0_HL_AL|ICTL_ICR0_CH0_EL_ET|
ICTL_ICR0_CH1_HL_AL|ICTL_ICR0_CH1_EL_ET|
ICTL_ICR0_CH2_HL_AL|ICTL_ICR0_CH2_EL_ET|
ICTL_ICR0_CH3_HL_AL|ICTL_ICR0_CH3_EL_ET|
ICTL_ICR0_CH4_HL_AL|ICTL_ICR0_CH4_EL_ET|
ICTL_ICR0_CH5_HL_AL|ICTL_ICR0_CH5_EL_ET);
HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICR1,
ICTL_ICR1_CH6_HL_AL|
ICTL_ICR1_CH7_HL_AL|
ICTL_ICR1_CH8_HL_AL);
HAL_WRITE_UINT32(CYG_DEVICE_ICTL_ICLR, 0xFFFF); // CLear all interrupts
HAL_WRITE_UINT32(CYG_DEVICE_ICTL_IRQER, 0x0000); // All disabled
// Clear and initialize cache
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
// Set up eCos/ROM interfaces
hal_if_init();
}
static void entry0( cyg_addrword_t data )
{
register CYG_INTERRUPT_STATE oldints;
#ifdef HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on");
time1();
#ifdef HAL_DCACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on: invalidate Cache (expect bogus timing)");
time1DI();
#endif
#else // HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off (again)");
time1();
#if defined(HAL_DCACHE_INVALIDATE_ALL) || defined(HAL_ICACHE_INVALIDATE_ALL)
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on (again)");
time1();
#if defined(CYGPKG_HAL_MIPS)
// In some architectures, the time taken for the next two tests is
// very long, partly because HAL_XCACHE_INVALIDATE_ALL() is implemented
// with a loop over the cache. Hence these tests take longer than the
// testing infrastructure is prepared to wait. The simplest way to get
// these tests to run quickly is to make them think they are running
// under a simulator.
// If the target actually is a simulator, skip the below - it's very
// slow on the simulator, even with reduced loop counts.
if (cyg_test_is_simulator)
CYG_TEST_PASS_FINISH("End of test");
#if defined(CYGPKG_HAL_MIPS_TX49)
// The TX49 has a large cache, and even with reduced loop count,
// 90+ seconds elapses between each INFO output.
CYG_TEST_PASS_FINISH("End of test");
#endif
cyg_test_is_simulator = 1;
#endif
#ifdef HAL_ICACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on: invalidate ICache each time");
time1II();
#endif
#ifdef HAL_DCACHE_INVALIDATE_ALL
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on: invalidate DCache (expect bogus times)");
time1DI();
#endif
#endif // either INVALIDATE_ALL macro
#endif // HAL_CACHE_UNIFIED
CYG_TEST_PASS_FINISH("End of test");
}
static void entry0( void )
{
register CYG_INTERRUPT_STATE oldints;
#ifdef HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL(); // rely on above definition
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Cache on");
time1();
#else // HAL_CACHE_UNIFIED
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache off");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache on Icache on");
time1();
HAL_DISABLE_INTERRUPTS(oldints);
HAL_DCACHE_PURGE_ALL();
HAL_ICACHE_INVALIDATE_ALL();
HAL_DCACHE_INVALIDATE_ALL();
HAL_ICACHE_DISABLE();
HAL_DCACHE_DISABLE();
HAL_RESTORE_INTERRUPTS(oldints);
CYG_TEST_INFO("Dcache off Icache off");
time1();
#endif // HAL_CACHE_UNIFIED
CYG_TEST_PASS_FINISH("End of test");
}
