/**
* @brief system software reset
*
* @return None
*
*/
void sys_reset(void)
{
// Set processor clock to default before system reset
HAL_WRITE32(SYSTEM_CTRL_BASE, 0x14, 0x00000021);
HalDelayUs(100*1000);
// Cortex-M3 SCB->AIRCR
HAL_WRITE32(0xE000ED00, 0x0C, (0x5FA << 16) | // VECTKEY
(HAL_READ32(0xE000ED00, 0x0C) & (7 << 8)) | // PRIGROUP
(1 << 2)); // SYSRESETREQ
}
/**
* MII Initialize.
*
* MII Initialize.
*
* Initialization Steps:
* I. Rtl8195A Board Configurations:
* 1. MII Function Enable & AHB mux
*
* @return runtime status value.
*/
BOOL
HalMiiGmacInitRtl8195a(
IN VOID *Data
)
{
u32 RegValue;
/* 1. enable MII Pinmux & disable SDIO Host/Device mode Pinmux */
RegValue = HAL_READ32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL);
RegValue |= BIT24;
RegValue &= ~(BIT0 | BIT1); // Important!
HAL_WRITE32(PERI_ON_BASE, REG_HCI_PINMUX_CTRL, RegValue);
/* 2. enable MII IP block (214, 12) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
RegValue |= BIT12;
HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
/* 3. Lexra2AHB Function Enable (304, 11) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
RegValue |= BIT11;
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
/* 4. enable MII bus clock (240, 24|25) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0);
RegValue |= (BIT24 | BIT25);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_HCI_CLK_CTRL0, RegValue);
/* 5. */
RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0x74) & 0xFFFFC7FF;
HAL_WRITE32(SYSTEM_CTRL_BASE, 0x74, (RegValue | 0x00003000));
/* 6. AHB mux: select MII (214, 13) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN);
RegValue |= BIT13;
HAL_WRITE32(PERI_ON_BASE, REG_SOC_HCI_COM_FUNC_EN, RegValue);
/* 7. Vendor Register Clock Enable (230, 6|7) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_CTRL);
RegValue |= (BIT6 | BIT7);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_CLK_CTRL, RegValue);
/* 8. Enable GMAC Lexra Timeout (090, 16|17|18) */
RegValue = HAL_READ32(VENDOR_REG_BASE, 0x0090);
RegValue |= (BIT16 | BIT17 | BIT18);
HAL_WRITE32(VENDOR_REG_BASE, 0x0090, RegValue);
/* 9. Endian Swap Control (304, 12|13) */
RegValue = HAL_READ32(PERI_ON_BASE, REG_PESOC_SOC_CTRL);
RegValue |= (BIT12 | BIT13);
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_SOC_CTRL, RegValue);
return _TRUE;
}
void ota_platform_reset(void)
{
//wifi_off();
// Set processor clock to default before system reset
HAL_WRITE32(SYSTEM_CTRL_BASE, 0x14, 0x00000021);
osDelay(100);
// Cortex-M3 SCB->AIRCR
HAL_WRITE32(0xE000ED00, 0x0C, (0x5FA << 16) | // VECTKEY
(HAL_READ32(0xE000ED00, 0x0C) & (7 << 8)) | // PRIGROUP
(1 << 2)); // SYSRESETREQ
while(1) osDelay(1000);
}
void __TRAP_HardFaultHandler_Patch(uint32_t addr)
{
uint32_t cfsr;
uint32_t bfar;
uint32_t stackpc;
uint16_t asmcode;
cfsr = HAL_READ32(0xE000ED28, 0x0);
// Violation to memory access protection
if (cfsr & 0x82) {
bfar = HAL_READ32(0xE000ED38, 0x0);
// invalid access to wifi register, usually happened in LPS 32K or IPS
if (bfar >= WIFI_REG_BASE && bfar < WIFI_REG_BASE + 0x40000) {
//__BKPT(0);
/* Get the MemManage fault PC, and step to next command.
* Otherwise it will keep hitting MemMange Fault on the same assembly code.
*
* To step to next command, we need parse the assembly code to check if
* it is 16-bit or 32-bit command.
* Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
* Chapter A6 - Thumb Instruction Set Encoding
*
* However, the fault assembly code (Ex. LDR or ADR) is not actually executed,
* So the register value is un-predictable.
**/
stackpc = HAL_READ32(addr, 0x18);
asmcode = HAL_READ16(stackpc, 0);
if ((asmcode & 0xF800) > 0xE000) {
// 32-bit instruction, (opcode[15:11] = 0b11111, 0b11110, 0b11101)
HAL_WRITE32(addr, 0x18, stackpc + 4);
} else {
// 16-bit instruction
HAL_WRITE32(addr, 0x18, stackpc + 2);
}
// clear Hard Fault Status Register
HAL_WRITE32(0xE000ED2C, 0x0, HAL_READ32(0xE000ED2C, 0x0));
return;
}
}
__TRAP_HardFaultHandler(addr);
}
/**
* @brief Clear the pending interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
)
{
u8 port_num;
u8 pin_num;
HAL_GPIO_PIN_MODE pin_mode;
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
pin_mode = GPIO_Pin->pin_mode;
if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) {
DBG_GPIO_ERR("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode);
return HAL_ERR_PARA;
}
if (GPIO_Lock() != HAL_OK) {
return HAL_BUSY;
}
// Clear pending interrupt before unmask it
HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<<pin_num));
GPIO_UnLock();
return HAL_OK;
}
void uartadapter_systemreload(void)
{
// Cortex-M3 SCB->AIRCR
HAL_WRITE32(0xE000ED00, 0x0C, (0x5FA << 16) | // VECTKEY
(HAL_READ32(0xE000ED00, 0x0C) & (7 << 8)) | // PRIGROUP
(1 << 2)); // SYSRESETREQ
}
static HAL_Status
RtkI2SPinMuxInit(
IN PHAL_I2S_ADAPTER pI2SAdapter
)
{
u32 I2Stemp;
if (pI2SAdapter->DevNum > I2S_MAX_ID) {
DBG_I2S_ERR("RtkI2SPinMuxInit: Invalid I2S Index(&d)\r\n", pI2SAdapter->DevNum);
return HAL_ERR_PARA;
}
// enable system pll
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
switch (pI2SAdapter->DevNum){
case I2S0_SEL:
ACTCK_I2S_CCTRL(ON);
SLPCK_I2S_CCTRL(ON);
LXBUS_FCTRL(ON); // enable lx bus for i2s
/*I2S0 Pin Mux Setting*/
PinCtrl(I2S0, pI2SAdapter->PinMux, ON);
if (pI2SAdapter->PinMux == I2S_S0) {
DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S0 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
}
I2S0_MCK_CTRL(ON);
I2S0_PIN_CTRL(ON);
I2S0_FCTRL(ON);
break;
case I2S1_SEL:
ACTCK_I2S_CCTRL(ON);
SLPCK_I2S_CCTRL(ON);
LXBUS_FCTRL(ON); // enable lx bus for i2s
/*I2S1 Pin Mux Setting*/
PinCtrl(I2S1, pI2SAdapter->PinMux, ON);
if (pI2SAdapter->PinMux == I2S_S2) {
DBG_I2S_WARN(ANSI_COLOR_MAGENTA"I2S1 Pin may conflict with JTAG\r\n"ANSI_COLOR_RESET);
}
I2S1_MCK_CTRL(ON);
I2S1_PIN_CTRL(ON);
I2S0_FCTRL(ON); //i2s 1 is control by bit 24 BIT_PERI_I2S0_EN
I2S1_FCTRL(ON);
break;
default:
return HAL_ERR_PARA;
}
return HAL_OK;
}
void Peripheral_Handler(void)
{
uint32_t PeriIrqStatus, CheckIndex, ExactIrqStatus, TableIndex;
PeriIrqStatus = PERIPHINT->STATUS;
/* For GPIO interrupt */
UINT32 gpio_int = 0x0;
UINT32 index = 0;
//Save exact IRQ status
ExactIrqStatus = PeriIrqStatus & (PERIPHINT->EN);
//Check exact IRQ function
for(CheckIndex = 0;CheckIndex<32;CheckIndex++)
{
if (ExactIrqStatus & BIT(CheckIndex))
{
if (CheckIndex == 0 ||
CheckIndex == 1 ||
CheckIndex == 2 ||
CheckIndex == 3 ||
CheckIndex == 4 ||
CheckIndex == 5 ||
CheckIndex == 6 ||
CheckIndex == 7 ||
CheckIndex == 8 ||
CheckIndex == 9
)
{
IRQ_FUN pFun = (IRQ_FUN)*(&__Vectors+ CheckIndex + 48);
pFun();
}
else if (CheckIndex == 16)
{
gpio_int = GPIO->INTSTATUS;
for (index = 6; index < 32; index++)
{
if(gpio_int&BIT(index))
{
IRQ_FUN pFun = (IRQ_FUN)*(&__Vectors+(52 + index));
pFun();
}
}
}
else
;
}
}
//Clear sub-rout IRQ
HAL_WRITE32(PERI_INT_REG_BASE, 0, PeriIrqStatus);
}
static RTK_STATUS
RtkDACPinMuxDeInit(
IN PSAL_DAC_HND pSalDACHND
){
u32 DACLocalTemp;
/* Check the I2C index first */
if (RtkDACIdxChk(pSalDACHND->DevNum))
return _EXIT_FAILURE;
switch (pSalDACHND->DevNum){
#if DAC0_USED
case DAC0_SEL:
{
/* Turn on DAC active clock */
ACTCK_DAC_CCTRL(OFF);
/* Enable DAC0 module */
DAC0_FCTRL(OFF);
break;
}
#endif
#if DAC1_USED
case DAC1_SEL:
{
/* Turn on DAC active clock */
ACTCK_DAC_CCTRL(OFF);
/* Enable DAC1 module */
DAC1_FCTRL(OFF);
break;
}
#endif
default:
return _EXIT_FAILURE;
}
DACLocalTemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2);
DACLocalTemp &= (~BIT26);
/* To release DAC delta sigma clock gating */
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_SYSPLL_CTRL2,DACLocalTemp);
return _EXIT_SUCCESS;
}
HAL_Status
RtkI2SDeInit(
IN VOID *Data
)
{
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
PHAL_I2S_INIT_DAT pI2SCfg;
u32 I2Stemp;
if (pI2SAdapter == 0) {
DBG_I2S_ERR("RtkI2SDeInit: Null Pointer\r\n");
return HAL_ERR_PARA;
}
pI2SCfg = pI2SAdapter->pInitDat;
/*I2S Disable Module*/
pI2SCfg->I2SEn = I2S_DISABLE;
pHalI2SOP->HalI2SEnable(pI2SCfg);
HalI2SClearAllOwnBit((VOID*)pI2SCfg);
/*I2C HAL DeInitialization*/
//pHalI2SOP->HalI2SDeInit(pI2SCfg);
/*I2S Interrupt DeInitialization*/
RtkI2SIrqDeInit(pI2SAdapter);
/*I2S Pin Mux DeInitialization*/
RtkI2SPinMuxDeInit(pI2SAdapter);
/*I2S HAL DeInitialization*/
pHalI2SOP->HalI2SDeInit(pI2SCfg);
/*I2S CLK Source Close*/
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10)));
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
/*I2S Device Status Update*/
pI2SAdapter->DevSts = I2S_STS_UNINITIAL;
return HAL_OK;
}
HAL_Status
RtkI2SEnable(
IN VOID *Data
)
{
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
PHAL_I2S_INIT_DAT pI2SCfg;
u32 I2Stemp;
// Enable IP Clock
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) | (1<<9) | (1<<10);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
ACTCK_I2S_CCTRL(ON);
SLPCK_I2S_CCTRL(ON);
pI2SCfg = pI2SAdapter->pInitDat;
pI2SCfg->I2SEn = I2S_ENABLE;
pHalI2SOP->HalI2SEnable(pI2SCfg);
return HAL_OK;
}
HAL_Status
RtkI2SDisable(
IN VOID *Data
)
{
PHAL_I2S_ADAPTER pI2SAdapter = (PHAL_I2S_ADAPTER) Data;
PHAL_I2S_OP pHalI2SOP = &HalI2SOpSAL;
PHAL_I2S_INIT_DAT pI2SCfg;
u32 I2Stemp;
pI2SCfg = pI2SAdapter->pInitDat;
pI2SCfg->I2SEn = I2S_DISABLE;
pHalI2SOP->HalI2SEnable(pI2SCfg);
// Gate IP Clock
ACTCK_I2S_CCTRL(OFF);
SLPCK_I2S_CCTRL(OFF);
// Close I2S bus clock(WS,SCLK,MCLK). If needs that clock, mark this.
I2Stemp = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & (~((1<<9) | (1<<10)));
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1, I2Stemp);
return HAL_OK;
}
HAL_Status
HalRuartInitRtl8195a_Patch(
IN VOID *Data ///< RUART Adapter
)
{
/* DBG_ENTRANCE; */
u32 RegValue;
u32 Divisor;
u32 Dll;
u32 Dlm;
u8 UartIndex;
s32 ElementIndex;
RUART_SPEED_SETTING RuartSpeedSetting;
u8 PinmuxSelect;
PHAL_RUART_ADAPTER pHalRuartAdapter = (PHAL_RUART_ADAPTER) Data;
UartIndex = pHalRuartAdapter->UartIndex;
PinmuxSelect = pHalRuartAdapter->PinmuxSelect;
if (UartIndex > 2) {
DBG_UART_ERR(ANSI_COLOR_MAGENTA"HalRuartInitRtl8195a: Invalid UART Index\n"ANSI_COLOR_RESET);
return HAL_ERR_PARA;
}
DBG_UART_INFO("%s==>\n", __FUNCTION__);
DBG_UART_INFO("HalRuartInitRtl8195a: [UART %d] PinSel=%d\n", UartIndex, PinmuxSelect);
if(( PinmuxSelect == RUART0_MUX_TO_GPIOE ) && ((UartIndex == 0) || (UartIndex == 1))) {
// confict with J-Teg pin, so we disable the J-Teg
DBG_UART_WARN(ANSI_COLOR_MAGENTA"Disable JTAG function due to pin conflict\n"ANSI_COLOR_RESET);
JTAG_PIN_FCTRL(OFF);
}
// switch Pin from EEPROM to UART0
if(( PinmuxSelect == RUART0_MUX_TO_GPIOC ) && (UartIndex == 0)) {
RegValue = HAL_READ32(SYSTEM_CTRL_BASE, 0xa4);
if (RegValue & 0x10) {
DBG_UART_WARN("Disable EEPROM Pin for UART 0\n");
HAL_WRITE32(SYSTEM_CTRL_BASE, 0xa4, (RegValue & (~0x10)));
}
}
switch (UartIndex) {
case 0:
/* UART 0 */
ACTCK_UART0_CCTRL(ON);
SLPCK_UART0_CCTRL(ON);
PinCtrl(UART0, PinmuxSelect, ON);
UART0_FCTRL(ON);
UART0_BD_FCTRL(ON);
break;
case 1:
/* UART 1 */
ACTCK_UART1_CCTRL(ON);
SLPCK_UART1_CCTRL(ON);
PinCtrl(UART1, PinmuxSelect, ON);
UART1_FCTRL(ON);
UART1_BD_FCTRL(ON);
break;
case 2:
/* UART 1 */
ACTCK_UART2_CCTRL(ON);
SLPCK_UART2_CCTRL(ON);
PinCtrl(UART2, PinmuxSelect, ON);
UART2_FCTRL(ON);
UART2_BD_FCTRL(ON);
break;
default:
DBG_UART_ERR("Invalid UART Index(%d)\n", UartIndex);
return HAL_ERR_PARA;
}
/* Reset RX FIFO */
HalRuartResetRxFifoRtl8195a(Data);
DBG_UART_INFO(ANSI_COLOR_CYAN"HAL UART Init[UART %d]\n"ANSI_COLOR_RESET, UartIndex);
/* Disable all interrupts */
HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, 0x00);
/* Set DLAB bit to 1 to access DLL/DLM */
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
RegValue |= RUART_LINE_CTL_REG_DLAB_ENABLE;
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
DBG_UART_INFO("[R] RUART_LINE_CTL_REG_OFF(0x0C) = %x\n", HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
/* Set Baudrate Division */
#if 1
ElementIndex = FindElementIndex(pHalRuartAdapter->BaudRate, BAUDRATE);
if (ElementIndex < 0) {
ElementIndex = 5;
DBG_UART_ERR("Invalid BaudRate(%d), Force it as default(%d)\n", pHalRuartAdapter->BaudRate, BAUDRATE[ElementIndex]);
}
RuartSpeedSetting.BaudRate = BAUDRATE[ElementIndex];
RuartSpeedSetting.Ovsr = OVSR_PATCH[ElementIndex];
RuartSpeedSetting.Div = DIV_PATCH[ElementIndex];
RuartSpeedSetting.Ovsr_adj = OVSR_ADJ_PATCH[ElementIndex];
#else
RuartSpeedSetting.BaudRate = 38400;
RuartSpeedSetting.Ovsr = 10;
RuartSpeedSetting.Div = 217;
RuartSpeedSetting.Ovsr_adj = 0x0;
#endif
DBG_UART_INFO("Baud %d, Ovsr %d, Div %d, OvsrAdj 0x%X\n",
RuartSpeedSetting.BaudRate,
RuartSpeedSetting.Ovsr,
RuartSpeedSetting.Div,
RuartSpeedSetting.Ovsr_adj
);
/* Divisor = (SYSTEM_CLK / ((ovsr + 5 + ovsr_adj/11) * (UartAdapter.BaudRate))); */
/* Set Divisor */
Divisor = RuartSpeedSetting.Div;
Dll = Divisor & 0xFF;
Dlm = (Divisor & 0xFF00) >> 8;
DBG_UART_INFO("Calculated Dll, Dlm = %02x, %02x\n", Dll, Dlm);
DBG_UART_INFO("---- Before setting baud rate ----\n");
DBG_UART_INFO(" [R] RUART_DLL_OFF(0x00) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLL_OFF));
DBG_UART_INFO(" [R] RUART_DLM_OFF(0x04) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLM_OFF));
HAL_RUART_WRITE32(UartIndex, RUART_DLL_OFF, Dll);
HAL_RUART_WRITE32(UartIndex, RUART_DLM_OFF, Dlm);
DBG_UART_INFO("---- After setting baud rate ----\n");
DBG_UART_INFO(" [R] RUART_DLL_OFF(0x00) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLL_OFF));
DBG_UART_INFO(" [R] RUART_DLM_OFF(0x04) = %x\n", HAL_RUART_READ32(UartIndex, RUART_DLM_OFF));
DBG_UART_INFO(ANSI_COLOR_CYAN"---- Befor OVSR & OVSR_ADJ ----\n"ANSI_COLOR_RESET);
RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
DBG_UART_INFO("UART%d SPR(0x1C) = %X\n", UartIndex, RegValue);
RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
DBG_UART_INFO("UART%d SIS(0x20) = %X\n", UartIndex, RegValue);
/**
* Clean Rx break signal interrupt status at initial stage.
*/
RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
RegValue |= RUART_SP_REG_RXBREAK_INT_STATUS;
HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue);
/* Set OVSR(xfactor) */
RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
RegValue &= ~(RUART_STS_REG_XFACTOR);
RegValue |= (((RuartSpeedSetting.Ovsr - 5) << 4) & RUART_STS_REG_XFACTOR);
HAL_RUART_WRITE32(UartIndex, RUART_STS_REG_OFF, RegValue);
/* Set OVSR_ADJ[10:0] (xfactor_adj[26:16]) */
RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
RegValue &= ~(RUART_SP_REG_XFACTOR_ADJ);
RegValue |= ((RuartSpeedSetting.Ovsr_adj << 16) & RUART_SP_REG_XFACTOR_ADJ);
HAL_RUART_WRITE32(UartIndex, RUART_SCRATCH_PAD_REG_OFF, RegValue);
DBG_UART_INFO(ANSI_COLOR_CYAN"---- After OVSR & OVSR_ADJ ----\n"ANSI_COLOR_RESET);
RegValue = HAL_RUART_READ32(UartIndex, RUART_SCRATCH_PAD_REG_OFF);
DBG_UART_INFO("UART%d SPR(0x1C) = %X\n", UartIndex, RegValue);
RegValue = HAL_RUART_READ32(UartIndex, RUART_STS_REG_OFF);
DBG_UART_INFO("UART%d SIS(0x20) = %X\n", UartIndex, RegValue);
/* clear DLAB bit */
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
RegValue &= ~(RUART_LINE_CTL_REG_DLAB_ENABLE);
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
DBG_UART_INFO("[R] RUART_LINE_CTL_REG_OFF(0x0C) = %x\n", HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
DBG_UART_INFO("[R] UART%d INT_EN(0x04) = %x\n", UartIndex, pHalRuartAdapter->Interrupts);
RegValue = ((pHalRuartAdapter->Interrupts) & 0xFF);
HAL_RUART_WRITE32(UartIndex, RUART_INTERRUPT_EN_REG_OFF, RegValue);
DBG_UART_INFO("[W] UART%d INT_EN(0x04) = %x\n", UartIndex, RegValue);
/* Configure FlowControl */
if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) {
RegValue = HAL_RUART_READ32(UartIndex, RUART_MODEM_CTL_REG_OFF);
RegValue |= RUART_MCL_AUTOFLOW_ENABLE;
HAL_RUART_WRITE32(UartIndex, RUART_MODEM_CTL_REG_OFF, RegValue);
}
/* RUART DMA Initialization */
HalRuartDmaInitRtl8195a(pHalRuartAdapter);
DBG_UART_INFO("[R] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
RegValue = HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF);
/* PARITY CONTROL */
RegValue &= BIT_CLR_LCR_WLS;
RegValue |= BIT_LCR_WLS(pHalRuartAdapter->WordLen);
RegValue &= BIT_INVC_LCR_STB_EN;
RegValue |= BIT_LCR_STB_EN(pHalRuartAdapter->StopBit);
RegValue &= BIT_INVC_LCR_PARITY_EN;
RegValue |= BIT_LCR_PARITY_EN(pHalRuartAdapter->Parity);
/* PARITY TYPE SELECT */
RegValue &= BIT_INVC_LCR_PARITY_TYPE;
RegValue |= BIT_LCR_PARITY_TYPE(pHalRuartAdapter->ParityType);
/* STICK PARITY CONTROL */
RegValue &= BIT_INVC_LCR_STICK_PARITY_EN;
RegValue |= BIT_LCR_STICK_PARITY_EN(pHalRuartAdapter->StickParity);
HAL_RUART_WRITE32(UartIndex, RUART_LINE_CTL_REG_OFF, RegValue);
DBG_UART_INFO("[W] UART%d LCR(0x%02X): %X\n", UartIndex, RUART_LINE_CTL_REG_OFF, HAL_RUART_READ32(UartIndex, RUART_LINE_CTL_REG_OFF));
/* Need to assert RTS during initial stage. */
if (pHalRuartAdapter->FlowControl == AUTOFLOW_ENABLE) {
HalRuartRTSCtrlRtl8195a(Data, 1);
}
pHalRuartAdapter->State = HAL_UART_STATE_READY;
return HAL_OK;
}
