static int __maybe_unused exynos_usb_hsic_init(struct platform_device *pdev) { u32 rstcon, hsic_ctrl; if (soc_is_exynos4212() || soc_is_exynos4412()) { exynos_usb_phy_control(USB_PHY_HSIC0 | USB_PHY_HSIC1, PHY_ENABLE); /* reset both PHY and Link of Host */ rstcon = readl(EXYNOS4_RSTCON) | EXYNOS4212_PHY1_HSIC0_SWRST | EXYNOS4212_PHY1_HSIC1_SWRST; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~(EXYNOS4212_PHY1_HSIC0_SWRST | EXYNOS4212_PHY1_HSIC1_SWRST); writel(rstcon, EXYNOS4_RSTCON); } else { /* HSIC phy reset */ hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) | HSIC_CTRL_PHYSWRST); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); udelay(10); hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); } return 0; }
static int exynos5_usb_phy20_exit(struct platform_device *pdev) { u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl; if (atomic_dec_return(&host_usage) > 0) { dev_info(&pdev->dev, "still being used\n"); return -EBUSY; } hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) | HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0); hostphy_ctrl0 |= (HOST_CTRL0_SIDDQ); hostphy_ctrl0 |= (HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); hostphy_ctrl0 |= (HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL); writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0); otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS); otgphy_sys |= (OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP); writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS); exynos_usb_phy_control(USB_PHY1, PHY_DISABLE); return 0; }
static int exynos5_usb_phy20_exit(struct platform_device *pdev) { u32 hostphy_ctrl0; u32 otgphy_sys; u32 hsic_ctrl; hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) | HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0); hostphy_ctrl0 |= (HOST_CTRL0_SIDDQ); hostphy_ctrl0 |= (HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); hostphy_ctrl0 |= (HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL); writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0); otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS); otgphy_sys |= (OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP); writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS); exynos4_usb_phy_control(USB_PHY1, PHY_DISABLE); return 0; }
static int __maybe_unused exynos_usb_hsic_exit(struct platform_device *pdev) { u32 hsic_ctrl; if (soc_is_exynos4212() || soc_is_exynos4412()) { exynos_usb_phy_control(USB_PHY_HSIC0 | USB_PHY_HSIC1, PHY_DISABLE); } else { hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) | HSIC_CTRL_SIDDQ | HSIC_CTRL_FORCESLEEP | HSIC_CTRL_FORCESUSPEND); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); } return 0; }
static int exynos5_usb_phy20_init(struct platform_device *pdev) { u32 refclk_freq; u32 hostphy_ctrl0, otgphy_sys, hsic_ctrl, ehcictrl, ohcictrl; atomic_inc(&host_usage); if (exynos5_usb_host_phy20_is_on()) { dev_err(&pdev->dev, "Already power on PHY\n"); return 0; } exynos_usb_mux_change(pdev, 1); exynos_usb_phy_control(USB_PHY1, PHY_ENABLE); /* Host and Device should be set at the same time */ hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0); hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK); otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS); otgphy_sys &= ~(OTG_SYS_CTRL0_FSEL_MASK); /* 2.0 phy reference clock configuration */ refclk_freq = exynos_usb_phy_set_clock(pdev); hostphy_ctrl0 |= (refclk_freq << HOST_CTRL0_CLKSEL_SHIFT); otgphy_sys |= (refclk_freq << OTG_SYS_CLKSEL_SHIFT); /* COMMON Block configuration during suspend */ hostphy_ctrl0 |= HOST_CTRL0_COMMONON_N; otgphy_sys &= ~(OTG_SYS_COMMON_ON); /* otg phy reset */ otgphy_sys &= ~(OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP); otgphy_sys &= ~(OTG_SYS_REF_CLK_SEL_MASK); otgphy_sys |= (OTG_SYS_REF_CLK_SEL(0x2) | OTG_SYS_OTGDISABLE); otgphy_sys |= (OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET); writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS); udelay(10); otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET); writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS); /* host phy reset */ hostphy_ctrl0 &= ~(HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL | HOST_CTRL0_SIDDQ); hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0); udelay(10); hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0); /* HSIC phy reset */ hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) | HSIC_CTRL_PHYSWRST); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); udelay(10); hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); udelay(80); /* enable EHCI DMA burst */ ehcictrl = readl(EXYNOS5_PHY_HOST_EHCICTRL); ehcictrl |= (EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 | EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16); writel(ehcictrl, EXYNOS5_PHY_HOST_EHCICTRL); /* set ohci_suspend_on_n */ ohcictrl = readl(EXYNOS5_PHY_HOST_OHCICTRL); ohcictrl |= OHCICTRL_SUSPLGCY; writel(ohcictrl, EXYNOS5_PHY_HOST_OHCICTRL); return 0; }
static int exynos5_usb_phy20_init(struct platform_device *pdev) { struct clk *ext_xtal; u32 refclk_freq; u32 hostphy_ctrl0; u32 otgphy_sys; u32 hsic_ctrl; u32 ehcictrl; exynos4_usb_phy_control(USB_PHY1, PHY_ENABLE); if (exynos5_usb_host_phy20_is_on()) { dev_err(&pdev->dev, "Already power on PHY\n"); return 0; } exynos_usb_mux_change(pdev, 1); /* Host and Device should be set at the same time */ hostphy_ctrl0 = readl(EXYNOS5_PHY_HOST_CTRL0); hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK); otgphy_sys = readl(EXYNOS5_PHY_OTG_SYS); otgphy_sys &= ~(OTG_SYS_CTRL0_FSEL_MASK); /* 2.0 phy reference clock configuration */ ext_xtal = clk_get(&pdev->dev, "ext_xtal"); switch (clk_get_rate(ext_xtal)) { case 96 * 100000: refclk_freq = EXYNOS5_CLKSEL_9600K; break; case 10 * MHZ: refclk_freq = EXYNOS5_CLKSEL_10M; break; case 12 * MHZ: refclk_freq = EXYNOS5_CLKSEL_12M; break; case 192 * 100000: refclk_freq = EXYNOS5_CLKSEL_19200K; break; case 20 * MHZ: refclk_freq = EXYNOS5_CLKSEL_20M; break; case 24 * MHZ: refclk_freq = EXYNOS5_CLKSEL_24M; break; default: case 50 * MHZ: /* default reference clock */ refclk_freq = EXYNOS5_CLKSEL_50M; break; } hostphy_ctrl0 |= (refclk_freq << HOST_CTRL0_CLKSEL_SHIFT); otgphy_sys |= (refclk_freq << OTG_SYS_CLKSEL_SHIFT); /* COMMON Block configuration during suspend */ hostphy_ctrl0 &= ~(HOST_CTRL0_COMMONON_N); otgphy_sys |= (OTG_SYS_COMMON_ON); /* otg phy reset */ otgphy_sys &= ~(OTG_SYS_FORCE_SUSPEND | OTG_SYS_SIDDQ_UOTG | OTG_SYS_FORCE_SLEEP); otgphy_sys &= ~(OTG_SYS_REF_CLK_SEL_MASK); otgphy_sys |= (OTG_SYS_REF_CLK_SEL(0x2) | OTG_SYS_OTGDISABLE); otgphy_sys |= (OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET); writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS); udelay(10); otgphy_sys &= ~(OTG_SYS_PHY0_SW_RST | OTG_SYS_LINK_SW_RST_UOTG | OTG_SYS_PHYLINK_SW_RESET); writel(otgphy_sys, EXYNOS5_PHY_OTG_SYS); /* host phy reset */ hostphy_ctrl0 &= ~(HOST_CTRL0_PHYSWRST | HOST_CTRL0_PHYSWRSTALL | HOST_CTRL0_SIDDQ); hostphy_ctrl0 &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); hostphy_ctrl0 |= (HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0); udelay(10); hostphy_ctrl0 &= ~(HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); writel(hostphy_ctrl0, EXYNOS5_PHY_HOST_CTRL0); /* HSIC phy reset */ hsic_ctrl = (HSIC_CTRL_REFCLKDIV(0x24) | HSIC_CTRL_REFCLKSEL(0x2) | HSIC_CTRL_PHYSWRST); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); udelay(10); hsic_ctrl &= ~(HSIC_CTRL_PHYSWRST); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL1); writel(hsic_ctrl, EXYNOS5_PHY_HSIC_CTRL2); udelay(80); ehcictrl = readl(EXYNOS5_PHY_HOST_EHCICTRL); ehcictrl |= (EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 | EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16); writel(ehcictrl, EXYNOS5_PHY_HOST_EHCICTRL); return 0; }