static sw_error_t
isis_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
{
a_uint32_t entry;
sw_error_t rv;
hsl_dev_t *pdev = NULL;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (S17_DEVICE_ID == entry) {
pdev->nr_ports = 7;
pdev->nr_phy = 5;
pdev->cpu_port_nr = 0;
pdev->nr_vlans = 4096;
pdev->hw_vlan_query = A_TRUE;
pdev->nr_queue = 6;
pdev->cpu_mode = cpu_mode;
} else {
pdev->nr_ports = 6;
pdev->nr_phy = 5;
pdev->cpu_port_nr = 0;
pdev->nr_vlans = 4096;
pdev->hw_vlan_query = A_TRUE;
pdev->nr_queue = 6;
pdev->cpu_mode = cpu_mode;
}
return SW_OK;
}
static sw_error_t
_shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t *enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == data)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
FORCE_PVLAN, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (val)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable)
{
sw_error_t rv;
a_uint32_t data;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (A_TRUE == enable) {
data &= (~((a_uint32_t)0x1 << port_id));
} else if (A_FALSE == enable) {
data |= (0x1 << port_id);
} else {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t reg, field;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
field = reg & (0x1 << port_id);
if (field) {
*enable = A_FALSE;
} else {
*enable = A_TRUE;
}
return SW_OK;
}
static sw_error_t
_garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t mem_port_id)
{
sw_error_t rv;
a_uint32_t regval = 0;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) (®val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
regval &= (~(0x1UL << mem_port_id));
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) (®val),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1qmode_t * pport_1qmode)
{
sw_error_t rv;
a_uint32_t regval = 0;
fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
FAL_1Q_CHECK, FAL_1Q_SECURE
};
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
SW_RTN_ON_NULL(pport_1qmode);
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
(a_uint8_t *) (®val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*pport_1qmode = retval[regval & 0x3];
return SW_OK;
}
static sw_error_t
_isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == val)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1q_egmode_t * pport_egvlanmode)
{
sw_error_t rv;
a_uint32_t regval = 0;
fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
FAL_EG_TAGGED
};
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
SW_RTN_ON_NULL(pport_egvlanmode);
HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
(a_uint8_t *) (®val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*pport_egvlanmode = retval[regval & 0x3];
return SW_OK;
}
static sw_error_t
_athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == val) {
*enable = A_TRUE;
} else {
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
athena_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
{
a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
sw_error_t rv;
while (vt_busy && --i) {
HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
(a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_udelay(5);
}
if (i == 0)
return SW_BUSY;
HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
(a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (vt_full) {
val = 0x10;
HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (VLAN_LOAD_ENTRY == op) {
return SW_FULL;
} else if (VLAN_PURGE_ENTRY == op) {
return SW_NOT_FOUND;
}
}
return SW_OK;
}
static sw_error_t
_dess_mib_op_commit(a_uint32_t dev_id, a_uint32_t op)
{
a_uint32_t mib_busy = 1, i = 0x1000, val;
sw_error_t rv;
while (mib_busy && --i)
{
HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
(a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_udelay(5);
}
if (i == 0)
return SW_BUSY;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_FUNC, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val);
SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val);
HSL_REG_ENTRY_SET(rv, dev_id, MIB_FUNC, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_busy = 1;
i = 0x1000;
while (mib_busy && --i)
{
HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
(a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_udelay(5);
}
if (i == 0)
return SW_FAIL;
return SW_OK;
}
static sw_error_t
_isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*port_id = val;
return SW_OK;
}
static sw_error_t
_shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*pts = val;
return SW_OK;
}
static sw_error_t
_horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*size = data;
return SW_OK;
}
static sw_error_t
_shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*time = data * 7;
return SW_OK;
}
static sw_error_t
_garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
TAG_VALUE, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
*tpid = val;
return SW_OK;
}
static sw_error_t
_isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
fal_port_t port_id, fal_stp_state_t * state)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (FAL_SINGLE_STP_ID != st_id)
{
return SW_BAD_PARAM;
}
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
switch (val)
{
case ISIS_STP_BLOCKING:
*state = FAL_STP_BLOKING;
break;
case ISIS_STP_LISTENING:
*state = FAL_STP_LISTENING;
break;
case ISIS_STP_LEARNING:
*state = FAL_STP_LEARNING;
break;
case ISIS_STP_FARWARDING:
*state = FAL_STP_FARWARDING;
break;
case ISIS_PORT_DISABLED:
*state = FAL_STP_DISABLED;
break;
default:
return SW_FAIL;
}
return SW_OK;
}
static sw_error_t
_horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == val) {
*enable = A_TRUE;
} else {
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (0 == val) {
*cmd = FAL_MAC_CPY_TO_CPU;
} else {
*cmd = FAL_MAC_RDT_TO_CPU;
}
return SW_OK;
}
static sw_error_t
_garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
*vid = val & 0xfff;
return rv;
}
static sw_error_t
_horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == val) {
*cmd = FAL_MAC_RDT_TO_CPU;
} else {
*cmd = FAL_MAC_FRWRD;
}
return SW_OK;
}
static sw_error_t
_horus_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == data) {
*enable = A_TRUE;
} else {
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (val) {
*enable = A_TRUE;
} else {
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_garuda_mc_leaky_mode_get(a_uint32_t dev_id,
fal_leaky_ctrl_mode_t *ctrl_mode)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == data) {
*ctrl_mode = FAL_LEAKY_FDB_CTRL;
} else {
*ctrl_mode = FAL_LEAKY_PORT_CTRL;
}
return SW_OK;
}
static sw_error_t
_garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pbmp_t * mem_port_map)
{
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
*mem_port_map = 0;
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) mem_port_map,
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
return SW_OK;
}
static sw_error_t
_shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == data)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == val)
{
*cmd = FAL_MAC_CPY_TO_CPU;
}
else
{
*cmd = FAL_MAC_RDT_TO_CPU;
}
return SW_OK;
}
static sw_error_t
_shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (val)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_dess_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (1 == val)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
