static sw_error_t
_isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_TRUE == enable)
{
data = 1;
}
else if (A_FALSE == enable)
{
data = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
FORCE_PVLAN, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_mc_leaky_mode_set(a_uint32_t dev_id,
fal_leaky_ctrl_mode_t ctrl_mode)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
{
data = 0;
}
else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
{
data = 1;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable)
{
sw_error_t rv;
a_uint32_t data;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (A_TRUE == enable) {
data &= (~((a_uint32_t)0x1 << port_id));
} else if (A_FALSE == enable) {
data |= (0x1 << port_id);
} else {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU)) {
return SW_BAD_PARAM;
}
if (A_TRUE == enable) {
val = 1;
} else if (A_FALSE == enable) {
val = 0;
} else {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE == enable)
{
data = 1;
}
else if (A_FALSE == enable)
{
data = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (FAL_MAC_CPY_TO_CPU == cmd)
{
val = 1;
}
else if (FAL_MAC_RDT_TO_CPU == cmd)
{
val = 0;
}
else
{
return SW_NOT_SUPPORTED;
}
HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1qmode_t port_1qmode)
{
sw_error_t rv;
a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (FAL_1Q_MODE_BUTT <= port_1qmode)
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
(a_uint8_t *) (®val[port_1qmode]),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_dess_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if ((0 == vid) || (vid > MAX_VLAN_ID))
{
return SW_BAD_PARAM;
}
val = vid;
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
fal_pbmp_t mem_port_map)
{
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_FALSE ==
hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t mem_port_id)
{
sw_error_t rv;
a_uint32_t regval = 0;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) (®val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
regval &= (~(0x1UL << mem_port_id));
HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
PORT_VID_MEM, (a_uint8_t *) (®val),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_dess_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
return rv;
}
static sw_error_t
_garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1q_egmode_t port_egvlanmode)
{
sw_error_t rv;
a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3 };
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (FAL_EG_MODE_BUTT <= port_egvlanmode)
{
return SW_BAD_PARAM;
}
if (FAL_EG_HYBRID == port_egvlanmode)
{
return SW_NOT_SUPPORTED;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
(a_uint8_t *) (®val[port_egvlanmode]),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
fal_pbmp_t member, fal_pbmp_t u_member)
{
#ifdef HSL_STANDALONG
sw_error_t rv;
a_int16_t loc;
a_uint32_t reg_tmp;
v_array_t *p_v_array;
fal_vlan_t *p_sw_vlan;
HSL_DEV_ID_CHECK(dev_id);
if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
return SW_OUT_OF_RANGE;
if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
return SW_BAD_PARAM;
if (u_member != 0)
return SW_BAD_PARAM;
if ((p_v_array = p_vlan_table[dev_id]) == NULL)
return SW_NOT_INITIALIZED;
rv = athena_vlan_table_location(dev_id, vlan_id, &loc);
SW_RTN_ON_ERROR(rv);
p_sw_vlan = &p_v_array[loc].vlan_entry;
/* set value for VLAN_TABLE_FUNC0, all 0 except vid */
reg_tmp = 0;
SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg_tmp);
SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN,
(a_int32_t)p_sw_vlan->vid_pri_en, reg_tmp);
SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, p_sw_vlan->vid_pri, reg_tmp);
HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
(a_uint8_t *) (®_tmp), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
/* set vlan member for VLAN_TABLE_FUNC1 */
HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
(a_uint8_t *) (&member), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
SW_RTN_ON_ERROR(rv);
p_v_array[loc].vlan_entry.mem_ports = member;
return SW_OK;
#else
return SW_NOT_SUPPORTED;
#endif
}
static sw_error_t
_garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
val = tpid;
HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
TAG_VALUE, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (HORUS_MAX_FRMAE_SIZE < size) {
return SW_BAD_PARAM;
}
data = size;
HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (port_id != MIRROR_ANALYZER_NONE) {
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
return SW_BAD_PARAM;
}
}
val = port_id;
HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
{
return SW_BAD_PARAM;
}
val = pts;
HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if ((65535 * 7 < *time) || (7 > *time))
{
return SW_BAD_PARAM;
}
data = *time / 7;
*time = data * 7;
HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
fal_port_t port_id, fal_stp_state_t state)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (FAL_SINGLE_STP_ID != st_id)
{
return SW_BAD_PARAM;
}
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
{
return SW_BAD_PARAM;
}
switch (state)
{
case FAL_STP_BLOKING:
val = ISIS_STP_BLOCKING;
break;
case FAL_STP_LISTENING:
val = ISIS_STP_LISTENING;
break;
case FAL_STP_LEARNING:
val = ISIS_STP_LEARNING;
break;
case FAL_STP_FARWARDING:
val = ISIS_STP_FARWARDING;
break;
case FAL_STP_DISABLED:
val = ISIS_PORT_DISABLED;
break;
default:
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
{
a_uint32_t data;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE == enable) {
data = 1;
} else if (A_FALSE == enable) {
data = 0;
} else {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_EN,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (FAL_MAC_FRWRD == cmd) {
val = 0;
} else if (FAL_MAC_RDT_TO_CPU == cmd) {
val = 1;
} else {
return SW_NOT_SUPPORTED;
}
HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE == enable) {
val = 1;
} else if (A_FALSE == enable) {
val = 0;
} else {
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_horus_reset(a_uint32_t dev_id)
{
#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
sw_error_t rv;
a_uint32_t val;
HSL_DEV_ID_CHECK(dev_id);
val = 0x1;
HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
rv = horus_hw_init(dev_id, horus_cfg[dev_id]);
SW_RTN_ON_ERROR(rv);
#endif
return SW_OK;
}
static sw_error_t
isis_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
hsl_dev_t *pdev = NULL;
a_uint32_t port_id;
a_uint32_t data;
sw_error_t rv;
pdev = hsl_dev_ptr_get(dev_id);
if (NULL == pdev) {
return SW_NOT_INITIALIZED;
}
/* Set default FDB hash mode as CRC10 */
data = 1;
HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, HASH_MODE,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
for (port_id = 0; port_id < pdev->nr_ports; port_id++) {
if (port_id == pdev->cpu_port_nr) {
continue;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
_athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
{
sw_error_t rv;
a_int16_t loc;
a_uint32_t reg_tmp;
#ifdef HSL_STANDALONG
v_array_t *p_v_array;
#endif
HSL_DEV_ID_CHECK(dev_id);
if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
return SW_OUT_OF_RANGE;
#ifdef HSL_STANDALONG
if ((p_v_array = p_vlan_table[dev_id]) == NULL)
return SW_NOT_INITIALIZED;
rv = athena_vlan_table_location(dev_id, vlan_id, &loc);
SW_RTN_ON_ERROR(rv);
#endif
reg_tmp = (a_int32_t) vlan_id;
HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
(a_uint8_t *) (®_tmp), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
rv = athena_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
SW_RTN_ON_ERROR(rv);
#ifdef HSL_STANDALONG
p_v_array[loc].active = A_FALSE;
#endif
return SW_OK;
}
static sw_error_t
_dess_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
{
a_uint32_t val;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_OUT_OF_RANGE;
}
if (port_id>7)
return SW_BAD_PARAM;
val = port_id;
HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_FLUSH_PORT,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
rv = _dess_mib_op_commit( dev_id, MIB_FLUSH_ONE_PORT);
return rv;
}