BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), /* 4706 variant quirks */ BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), /* 4331 quirks*/ BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), /* 4360 quirks */ BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), BHND_DEVICE_QUIRK_END }; // FIXME: IRQ shouldn't be hard-coded #define CHIPC_MIPS_IRQ 2 static int chipc_add_children(struct chipc_softc *sc); static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps); static int chipc_read_caps(struct chipc_softc *sc,
struct resource *m_res; /**< resource containing the register window, or NULL if no window mapped */
bhnd_addr_t m_target; /**< base address mapped by m_win */
bhnd_addr_t m_addr; /**< mapped address */
bhnd_size_t m_size; /**< mapped size */
bool m_valid; /**< true if a valid mapping exists, false otherwise */
struct bhndb_host_resources *hr; /**< backing host resources */
};
static struct bhndb_pci_quirk bhndb_pci_quirks[] = {
/* Backplane interrupt flags must be routed via siba-specific
* SIBA_CFG0_INTVEC configuration register; the BHNDB_PCI_INT_MASK
* PCI configuration register is unsupported. */
{{ BHND_MATCH_CHIP_TYPE (SIBA) },
{ BHND_MATCH_CORE_REV (HWREV_LTE(5)) },
BHNDB_PCI_QUIRK_SIBA_INTVEC },
/* All PCI core revisions require the SRSH work-around */
BHNDB_PCI_QUIRK(HWREV_ANY, BHNDB_PCI_QUIRK_SRSH_WAR),
BHNDB_PCI_QUIRK_END
};
static struct bhndb_pci_quirk bhndb_pcie_quirks[] = {
/* All PCIe-G1 core revisions require the SRSH work-around */
BHNDB_PCI_QUIRK(HWREV_ANY, BHNDB_PCI_QUIRK_SRSH_WAR),
BHNDB_PCI_QUIRK_END
};
static struct bhndb_pci_quirk bhndb_pcie2_quirks[] = {
BHNDB_PCI_QUIRK_END
