static irqreturn_t pv_isr(int irq, void *dev_data)
{
u32 pv_base, irq_stat;
struct pv_dev *dev = dev_data;
pv_base = dev->base_addr;
irq_stat = readl(pv_base + REG_PV_INTSTAT);
printk("0x%x\n", irq_stat);
u32 read_stat = irq_stat;
#ifdef INT_4_LONG_PKT
if(irq_stat & VFP_START) {
printk("Debug: shouldn't have come here for CMND_WHEN_VBP\n");
if (pkt_ready) {
pkt_ready = 0;
u32 pktc_addr = HW_IO_PHYS_TO_VIRT(0x3c200004);
u32 pktc_val = readl(pktc_addr);
writel((pktc_val | 1), pktc_addr);
if(! (readl(pv_base + REG_PV_STAT) & VFP))
printk("trig -");
else
printk("trig +\n");
}
irq_stat &= ~VFP_START;
writel(VFP_START, pv_base + REG_PV_INTSTAT);
}
#endif
// pr_info("pv_isr 0x%x\n", read_stat);
if (irq_stat & VFP_END) {
if (PV_STOPPING == dev->state) {
writel(readl(pv_base + REG_PV_C) & ~PVEN,
pv_base + REG_PV_C);
/*Change PV state to Stopped*/
dev->state = PV_STOPPED;
schedule_work(&dev->eof_work);
}
writel(VFP_END, pv_base + REG_PV_INTSTAT);
irq_stat = irq_stat & ~VFP_END;
//disable_irq(dev->irq);
}
if (irq_stat & OF_UF) {
dev->irq_stat |= OF_UF;
schedule_work(&dev->err_work);
writel(HVS_UF | HVS_OF | PV_UF, pv_base + REG_PV_STAT);
writel(OF_UF, pv_base + REG_PV_INTSTAT);
irq_stat = irq_stat & ~OF_UF;
}
if (irq_stat) {
writel(irq_stat, pv_base + REG_PV_INTSTAT);
}
return IRQ_HANDLED;
}
static int bcm_hsotgctrl_probe(struct platform_device *pdev)
{
int error = 0;
unsigned int val;
struct bcm_hsotgctrl_drv_data *hsotgctrl_drvdata;
struct bcm_hsotgctrl_platform_data *plat_data = NULL;
if (pdev->dev.platform_data)
plat_data = (struct bcm_hsotgctrl_platform_data *)
pdev->dev.platform_data;
else if (pdev->dev.of_node) {
int val;
struct resource *resource;
plat_data = kzalloc(sizeof(struct bcm_hsotgctrl_platform_data),
GFP_KERNEL);
if (!plat_data) {
dev_err(&pdev->dev,
"%s: memory allocation failed.", __func__);
error = -ENOMEM;
goto err_ret;
}
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (resource->start)
plat_data->hsotgctrl_virtual_mem_base =
HW_IO_PHYS_TO_VIRT(resource->start);
else {
pr_info("Invalid hsotgctrl_virtual_mem_basei from DT\n");
goto err_read;
}
if (of_property_read_u32(pdev->dev.of_node,
"chipreg-virtual-mem-base", &val)) {
error = -EINVAL;
dev_err(&pdev->dev, "chipreg-virtual-mem-base read failed\n");
goto err_read;
}
plat_data->chipreg_virtual_mem_base = HW_IO_PHYS_TO_VIRT(val);
resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (resource->start)
plat_data->irq = resource->start;
else {
pr_info("Invalid irq from DT\n");
goto err_read;
}
if (of_property_read_string(pdev->dev.of_node,
"usb-ahb-clk-name",
&plat_data->usb_ahb_clk_name) != 0) {
error = -EINVAL;
dev_err(&pdev->dev, "usb-ahb-clk-name read failed\n");
goto err_read;
}
if (of_property_read_string(pdev->dev.of_node,
"mdio-mstr-clk-name",
&plat_data->mdio_mstr_clk_name) != 0) {
error = -EINVAL;
dev_err(&pdev->dev, "mdio-mstr-clk-name read failed\n");
goto err_read;
}
}
if (plat_data == NULL) {
dev_err(&pdev->dev, "platform_data failed\n");
return -ENODEV;
}
hsotgctrl_drvdata = kzalloc(sizeof(*hsotgctrl_drvdata), GFP_KERNEL);
if (!hsotgctrl_drvdata) {
dev_warn(&pdev->dev, "Memory allocation failed\n");
return -ENOMEM;
}
local_hsotgctrl_handle = hsotgctrl_drvdata;
hsotgctrl_drvdata->hsotg_ctrl_base =
(void *)plat_data->hsotgctrl_virtual_mem_base;
if (!hsotgctrl_drvdata->hsotg_ctrl_base) {
dev_warn(&pdev->dev, "No vaddr for HSOTGCTRL!\n");
goto error_get_vaddr;
}
hsotgctrl_drvdata->chipregs_base =
(void *)plat_data->chipreg_virtual_mem_base;
if (!hsotgctrl_drvdata->chipregs_base) {
dev_warn(&pdev->dev, "No vaddr for CHIPREG!\n");
goto error_get_vaddr;
}
hsotgctrl_drvdata->dev = &pdev->dev;
hsotgctrl_drvdata->otg_clk = clk_get(NULL,
plat_data->usb_ahb_clk_name);
if (IS_ERR(hsotgctrl_drvdata->otg_clk)) {
error = PTR_ERR(hsotgctrl_drvdata->otg_clk);
dev_warn(&pdev->dev,
"OTG clock allocation failed - %d\n", error);
goto error_get_otg_clk;
}
hsotgctrl_drvdata->mdio_master_clk = clk_get(NULL,
plat_data->mdio_mstr_clk_name);
if (IS_ERR(hsotgctrl_drvdata->mdio_master_clk)) {
error = PTR_ERR(hsotgctrl_drvdata->mdio_master_clk);
dev_warn(&pdev->dev,
"MDIO Mst clk alloc failed - %d\n", error);
goto error_get_master_clk;
}
hsotgctrl_drvdata->allow_suspend = true;
platform_set_drvdata(pdev, hsotgctrl_drvdata);
bcm_hsotgctrl_en_clock(true);
mdelay(HSOTGCTRL_STEP_DELAY_IN_MS);
/* clear bit 15 RDB error */
val = readl(hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_PHY_P1CTL_OFFSET);
val &= ~HSOTG_CTRL_PHY_P1CTL_USB11_OEB_IS_TXEB_MASK;
writel(val, hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_PHY_P1CTL_OFFSET);
mdelay(HSOTGCTRL_STEP_DELAY_IN_MS);
/* S/W reset Phy, active low */
val = readl(hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_PHY_P1CTL_OFFSET);
val &= ~HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK;
writel(val, hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_PHY_P1CTL_OFFSET);
mdelay(HSOTGCTRL_STEP_DELAY_IN_MS);
/* bring Phy out of reset */
val = readl(hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_PHY_P1CTL_OFFSET);
val &= ~HSOTG_CTRL_PHY_P1CTL_PHY_MODE_MASK;
val |= HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK;
/* use OTG mode */
val |= PHY_MODE_OTG << HSOTG_CTRL_PHY_P1CTL_PHY_MODE_SHIFT;
writel(val, hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_PHY_P1CTL_OFFSET);
mdelay(HSOTGCTRL_STEP_DELAY_IN_MS);
/* Enable pad, internal PLL etc */
bcm_hsotgctrl_set_phy_off(false);
mdelay(HSOTGCTRL_STEP_DELAY_IN_MS);
/*Come up as device until we check PMU ID status
* to avoid turning on Vbus before checking
*/
val = HSOTG_CTRL_USBOTGCONTROL_OTGSTAT_CTRL_MASK |
HSOTG_CTRL_USBOTGCONTROL_UTMIOTG_IDDIG_SW_MASK |
HSOTG_CTRL_USBOTGCONTROL_USB_HCLK_EN_DIRECT_MASK |
HSOTG_CTRL_USBOTGCONTROL_USB_ON_IS_HCLK_EN_MASK |
HSOTG_CTRL_USBOTGCONTROL_USB_ON_MASK |
HSOTG_CTRL_USBOTGCONTROL_PRST_N_SW_MASK |
HSOTG_CTRL_USBOTGCONTROL_HRESET_N_SW_MASK;
writel(val, hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_USBOTGCONTROL_OFFSET);
mdelay(HSOTGCTRL_STEP_DELAY_IN_MS);
error = device_create_file(&pdev->dev, &dev_attr_hsotgctrldump);
if (error) {
dev_warn(&pdev->dev, "Failed to create HOST file\n");
goto Error_bcm_hsotgctrl_probe;
}
#ifndef CONFIG_USB_OTG_UTILS
/* Clear non-driving as default in case there
* is no transceiver hookup */
bcm_hsotgctrl_phy_set_non_driving(false);
#endif
#ifdef CONFIG_NOP_USB_XCEIV
/* Clear non-driving as default in case there
* is no transceiver hookup */
bcm_hsotgctrl_phy_set_non_driving(false);
#endif
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
hsotgctrl_drvdata->hsotgctrl_irq = platform_get_irq(pdev, 0);
/* Create a work queue for wakeup work items */
hsotgctrl_drvdata->bcm_hsotgctrl_work_queue =
create_workqueue("bcm_hsotgctrl_events");
if (hsotgctrl_drvdata->bcm_hsotgctrl_work_queue == NULL) {
dev_warn(&pdev->dev,
"BCM HSOTGCTRL events work queue creation failed\n");
/* Treat this as non-fatal error */
}
INIT_DELAYED_WORK(&hsotgctrl_drvdata->wakeup_work,
bcm_hsotgctrl_delayed_wakeup_handler);
/* disable Bvalid interrupt bit
* This interrupt is not currently used as the STAT2 detection
* happens from the PMU side. Beacsue of not clearing this bit
* Master clock gating feature was not working in Java. This
* is not a issue in case of Hawaii
* */
val = readl(hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_USBOTGCONTROL_OFFSET);
val |= 1 << HSOTG_CTRL_USBOTGCONTROL_BVALID_CLR_SHIFT;
writel(val, hsotgctrl_drvdata->hsotg_ctrl_base +
HSOTG_CTRL_USBOTGCONTROL_OFFSET);
bcm_hsotgctrl_en_clock(false);
/* request_irq enables irq */
hsotgctrl_drvdata->irq_enabled = true;
error = request_irq(hsotgctrl_drvdata->hsotgctrl_irq,
bcm_hsotgctrl_wake_irq,
IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND,
"bcm_hsotgctrl", (void *)hsotgctrl_drvdata);
if (error) {
hsotgctrl_drvdata->irq_enabled = false;
hsotgctrl_drvdata->hsotgctrl_irq = 0;
dev_warn(&pdev->dev, "Failed to request IRQ for wakeup\n");
}
return 0;
Error_bcm_hsotgctrl_probe:
clk_put(hsotgctrl_drvdata->mdio_master_clk);
bcm_hsotgctrl_en_clock(false);
error_get_master_clk:
clk_put(hsotgctrl_drvdata->otg_clk);
error_get_otg_clk:
error_get_vaddr:
kfree(hsotgctrl_drvdata);
err_read:
if (pdev->dev.of_node)
kfree(plat_data);
err_ret:
pr_err("%s probe failed\n", __func__);
return error;
}
{BCM_KEY_ROW_6, BCM_KEY_COL_7, "unused", 0},
{BCM_KEY_ROW_7, BCM_KEY_COL_0, "unused", 0},
{BCM_KEY_ROW_7, BCM_KEY_COL_1, "unused", 0},
{BCM_KEY_ROW_7, BCM_KEY_COL_2, "unused", 0},
{BCM_KEY_ROW_7, BCM_KEY_COL_3, "unused", 0},
{BCM_KEY_ROW_7, BCM_KEY_COL_4, "unused", 0},
{BCM_KEY_ROW_7, BCM_KEY_COL_5, "unused", 0},
{BCM_KEY_ROW_7, BCM_KEY_COL_6, "unused", 0},
{BCM_KEY_ROW_7, BCM_KEY_COL_7, "unused", 0},
};
static struct bcm_keypad_platform_info hawaii_keypad_data = {
.row_num = 1,
.col_num = 4,
.keymap = hawaii_keymap,
.bcm_keypad_base = (void *)__iomem HW_IO_PHYS_TO_VIRT(KEYPAD_BASE_ADDR),
};
#endif
#define GPIO_KEYS_SETTINGS { { KEY_HOME, 10, 1, "HOME", EV_KEY, 0, 64}, }
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
static struct gpio_keys_button board_gpio_keys[] = GPIO_KEYS_SETTINGS;
static struct gpio_keys_platform_data gpio_keys_data = {
.nbuttons = ARRAY_SIZE(board_gpio_keys),
.buttons = board_gpio_keys,
};
static struct platform_device board_gpio_keys_device = {
.flags = KONA_CPUFREQ_UPDATE_LPJ | KONA_CPUFREQ_TMON,
};
struct platform_device kona_cpufreq_device = {
.name = "kona-cpufreq-drv",
.id = -1,
.dev = {
.platform_data = &kona_cpufreq_drv_pdata,
},
};
#endif /*CONFIG_KONA_CPU_FREQ_DRV */
#ifdef CONFIG_KONA_AVS
static struct avs_pdata avs_pdata = {
.avs_info_base_addr = HW_IO_PHYS_TO_VIRT(0x3404E39C),
.a7_regl_name = "csr_uc",
.pwrwdog_base = KONA_PWRWDOG_VA,
.irdrop_vreq = 1200000,
};
struct platform_device avs_device = {
.name = "avs",
.id = -1,
.dev = {
.platform_data = &avs_pdata,
}
};
#endif
#ifdef CONFIG_KONA_MEMC
static int h264_open(struct inode *inode, struct file *filp)
{
int ret = 0;
struct h264_t *dev = kmalloc(sizeof(struct h264_t), GFP_KERNEL);
if (!dev) {
printk("\n Returning from no memory");
return -ENOMEM;
}
mutex_lock(&h264_mutex);
filp->private_data = dev;
spin_lock_init(&dev->lock);
dev->dev_status.cbc_intr = 0x00;
dev->dev_status.mcin_intr = 0x00;
init_completion(&dev->irq_sem);
/*
Add a request for DFS.
Add a request for QOS (with default value)
Enable the clock for H.264 block.
*/
#ifdef H264_CLK_MGMT
ret =
pi_mgr_dfs_add_request(&h264_dfs_node, "h264", PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI DFS request\n",
__func__);
goto err;
}
#ifdef H264_QOS_MGMT
ret =
pi_mgr_qos_add_request(&h264_qos_node, "h264",
PI_MGR_PI_ID_ARM_CORE,
PI_MGR_QOS_DEFAULT_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI QOS request\n",
__func__);
ret = -EIO;
goto qos_request_fail;
}
#endif
enable_h264_clock();
/* Access to root reset manager register block. */
writel(0xa5a501, IOMEM(HW_IO_PHYS_TO_VIRT(0x35001f00)));
usleep_range(10, 20);
/* Enable multimedia power domain. */
/* Test 0x3d should be sufficient for MM. */
writel(0xfd, IOMEM(HW_IO_PHYS_TO_VIRT(0x35001f08)));
usleep_range(10, 20);
/* Enable H264 Slave interface control register. */
writel(0x00, IOMEM(HW_IO_PHYS_TO_VIRT(0x3C00F004)));
usleep_range(10, 20);
/* Enable H264 Master interface control register. */
writel(0x00, IOMEM(HW_IO_PHYS_TO_VIRT(0x3C00F008)));
usleep_range(10, 20);
#ifdef H264_QOS_MGMT
ret = pi_mgr_qos_request_update(&h264_qos_node, 0);
if (ret) {
printk(KERN_ERR "%s: failed to register PI QOS request\n",
__func__);
ret = -EIO;
}
scu_standby(0);
#endif
#endif
usleep_range(50, 100); /* buffer to ensure everything above are done. */
#ifdef ENABLE_H264_INT
/* Register for the interrupts */
ret =
request_irq(H264_AOB_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED |
IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for AOB ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_AOB_IRQ, cpumask_of(0));
ret =
request_irq(H264_CME_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED |
IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for CME ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_CME_IRQ, cpumask_of(0));
ret =
request_irq(H264_MCIN_CBC_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED
| IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for MCIN_CBC ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_MCIN_CBC_IRQ, cpumask_of(0));
disable_irq(H264_AOB_IRQ);
disable_irq(H264_CME_IRQ);
disable_irq(H264_MCIN_CBC_IRQ);
#endif
return 0;
#ifdef H264_QOS_MGMT
qos_request_fail:
pi_mgr_dfs_request_remove(&h264_dfs_node);
#endif
err:
kfree(dev);
printk(KERN_ERR "\nError in the h264_open\n");
mutex_unlock(&h264_mutex);
return ret;
}
struct ccu_profiler *capri_ccu_profiler_tbl[] = {
&CCU_PROFILER(khub),
&CCU_PROFILER(root),
&CCU_PROFILER(kpm),
&CCU_PROFILER(kps),
&CCU_PROFILER(kproc),
};
/**
* ARM island PI ON Profiler
*/
DEFINE_PI_PROFILER(arm) = {
.profiler = {
.name = "pi_arm",.owner = THIS_MODULE,},.pi_prof_addr_base =
HW_IO_PHYS_TO_VIRT(PWRMGR_BASE_ADDR),.pi_id =
PI_MGR_PI_ID_ARM_CORE,.counter_offset =
PWRMGR_PI_ARM_CORE_ON_COUNTER_OFFSET,.counter_en_mask =
PWRMGR_PI_ARM_CORE_ON_COUNTER_PI_ARM_CORE_ON_COUNTER_ENABLE_MASK,.
counter_mask =
PWRMGR_PI_ARM_CORE_ON_COUNTER_PI_ARM_CORE_ON_COUNTER_MASK,.
overflow_mask =
PWRMGR_PI_ARM_CORE_ON_COUNTER_PI_ARM_CORE_ON_COUNTER_OVERFLOW_MASK,.
counter_en_shift =
PWRMGR_PI_ARM_CORE_ON_COUNTER_PI_ARM_CORE_ON_COUNTER_ENABLE_SHIFT,.
counter_shift =
PWRMGR_PI_ARM_CORE_ON_COUNTER_PI_ARM_CORE_ON_COUNTER_SHIFT,.
counter_clear_offset =
PWRMGR_PC_PIN_OVERRIDE_CONTROL_OFFSET,.counter_clear_mask =
PWRMGR_PC_PIN_OVERRIDE_CONTROL_CLEAR_PI_COUNTERS_MASK,.
counter_clear_shift =
