int8 tunerbb_drv_t39fx_get_fic(uint8* buffer, uint32* buffer_size /*, boolean cr_onoff */)
{
INC_UINT32 uiFicSize;
if(buffer == NULL || buffer_size == NULL)
{
return INC_ERROR;
}
if(!(INC_CMD_READ(TDMB_RFBB_DEV_ADDR, APB_VTB_BASE+ 0x00) & 0x4000))
{
*buffer_size = 0;
return INC_ERROR;
}
uiFicSize = (INC_UINT32)INC_CMD_READ(TDMB_RFBB_DEV_ADDR, APB_VTB_BASE+ 0x09) +1;
if(uiFicSize == 1)
{
*buffer_size = 0;
return INC_ERROR;
}
if(uiFicSize > 384)
{
printk("tunerbb_drv_t39fx_get_fic uiFicSize = (%d) is over 384\n", uiFicSize);
uiFicSize = 384;
}
if(INC_CMD_READ_BURST(TDMB_RFBB_DEV_ADDR, APB_FIC_BASE, buffer, uiFicSize) == INC_SUCCESS)
{
*buffer_size = uiFicSize;
printk("tunerbb_drv_t39fx_get_fic = %x %x %x %x %x\n", *buffer, *(buffer+1), *(buffer+2), *(buffer+3), *(buffer+4));
return INC_SUCCESS;
}
return INC_ERROR;
}
/* 인터럽트 서비스 루틴... // SPI Slave Mode or MPI Slave Mode */
INC_UINT8 INTERFACE_ISR(INC_UINT8 ucI2CID, INC_UINT8* pBuff)
{
INC_UINT16 unDataLength;
unDataLength = INC_CMD_READ(ucI2CID, APB_MPI_BASE+0x6);
if(unDataLength < INC_INTERRUPT_SIZE)
{
return INC_ERROR;
}
INC_CMD_READ_BURST(ucI2CID, APB_STREAM_BASE, pBuff, INC_INTERRUPT_SIZE);
if((m_unIntCtrl & INC_INTERRUPT_LEVEL) && (!(m_unIntCtrl & INC_INTERRUPT_AUTOCLEAR_ENABLE)))
INTERFACE_INT_CLEAR(ucI2CID, INC_MPI_INTERRUPT_ENABLE);
return INC_SUCCESS;
}
int8 tunerbb_drv_t39fx_check_tii(uint8* pmain_tii, uint8* psub_tii)
{
ST_TII_INFO stTIIInfo[MAX_TII_CNT] = {{0,},};
INC_UINT16 uiStatus = 0;
uiStatus = INC_CMD_READ(TDMB_RFBB_DEV_ADDR, APB_PHY_BASE+ 0x2D);
if(uiStatus == 0x1F7F) return INC_ERROR;
INC_TII_GET_INFO(TDMB_RFBB_DEV_ADDR,stTIIInfo);
printk(" ==> TII0 [MainID(0x%X), SubID(0x%X), Strength(%d)] \n", stTIIInfo[0].uiPattern, stTIIInfo[0].uiSubID, stTIIInfo[0].uiStrength);
*pmain_tii = (uint8)stTIIInfo[0].uiPattern;
*psub_tii = (uint8)stTIIInfo[0].uiSubID;
return INC_SUCCESS;
}
void tunerbb_drv_t39fx_rw_test(void)
{
unsigned short i = 0;
unsigned short w_val = 0;
unsigned short r_val = 0;
unsigned short err_cnt = 0;
err_cnt = 0;
for(i=1;i<11;i++)
{
w_val = (i%0xFF);
INC_CMD_WRITE(TDMB_RFBB_DEV_ADDR, 0x0A00+ 0x05, w_val) ;
r_val = INC_CMD_READ(TDMB_RFBB_DEV_ADDR, 0x0A00+ 0x05);
if(r_val != w_val)
{
err_cnt++;
printk("w_val:%x, r_val:%x\n", w_val,r_val);
}
if(err_cnt == 0)
printk("t39fx interface test ok...\n");
}
}
void tunerbb_drv_lg2102_rw_test(void)
{
unsigned short i = 0;
unsigned short w_val = 0;
unsigned short r_val = 0;
unsigned short err_cnt = 0;
err_cnt = 0;
for(i=1;i<30;i++)
{
w_val = (i%0xFF);
INC_CMD_WRITE(TDMB_RFBB_DEV_ADDR, 0x0A00+ 0x01, w_val) ;;
r_val = INC_CMD_READ(TDMB_RFBB_DEV_ADDR, 0x0A00+ 0x01);
if(r_val != w_val)
{
err_cnt++;
printk("[rw fail] w_val:%x, r_val:%x, err_cnt = %d\n", w_val,r_val,err_cnt);
}
if(err_cnt == 0){
printk("lg2102 interface test ok...\n");
}
}
}
void INTERFACE_INC_DEBUG(INC_UINT8 ucI2CID)
{
unsigned int nLoop = 0;
for(nLoop = 0; nLoop < 3; nLoop++)
{
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_DEINT_BASE+ 0x02+%d : 0x%X \r\n", nLoop*2, INC_CMD_READ(TDMB_I2C_ID80, APB_DEINT_BASE+ 0x02 + (nLoop*2)));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_DEINT_BASE+ 0x03+%d : 0x%X \r\n", nLoop*2, INC_CMD_READ(TDMB_I2C_ID80, APB_DEINT_BASE + 0x03 + (nLoop*2)));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_VTB_BASE + 0x02+%d : 0x%X \r\n", nLoop, INC_CMD_READ(TDMB_I2C_ID80, APB_VTB_BASE+ 0x02 + nLoop));
}
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x00 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x00));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x01 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x01));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x02 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x02));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x03 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x03));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x04 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x04));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x05 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x05));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x06 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x06));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x07 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x07));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_MPI_BASE+ 0x08 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_MPI_BASE + 0x08));
// INIT
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_INT_BASE+ 0x00 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_INT_BASE + 0x00));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_INT_BASE+ 0x01 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_INT_BASE + 0x01));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_INT_BASE+ 0x02 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_INT_BASE + 0x02));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_INT_BASE+ 0x03 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_INT_BASE + 0x03));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x3B : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x3B));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x00 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x00));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x84 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x84));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x86 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x86));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xB4 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xB4));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x1A : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x1A));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x8A : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x8A));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xC4 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xC4));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x24 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x24));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xBE : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xBE));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xB0 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xB0));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xC0 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xC0));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x8C : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x8C));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xA8 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xA8));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xAA : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xAA));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x80 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x80));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x88 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x88));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xC8 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xC8));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xBC : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xBC));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x90 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x90));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xCA : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xCA));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x40 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x40));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x24 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x24));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0x41 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0x41));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_PHY_BASE+ 0xC6 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_PHY_BASE + 0xC6));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_VTB_BASE+ 0x05 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_VTB_BASE + 0x05));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_VTB_BASE+ 0x01 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_VTB_BASE + 0x01));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_VTB_BASE+ 0x00 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_VTB_BASE + 0x00));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_RS_BASE+ 0x00 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_RS_BASE + 0x00));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_RS_BASE+ 0x07 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_RS_BASE + 0x07));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_RS_BASE+ 0x0A : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_RS_BASE + 0x0A));
INC_MSG_PRINTF(INC_DEBUG_LEVEL, " APB_RS_BASE+ 0x01 : 0x%X \r\n", INC_CMD_READ(TDMB_I2C_ID80, APB_RS_BASE + 0x01));
}
