int32_t instr_group_3_f6_not(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if (i->modrm.mod != 3)
{
/* F6 /2
* Reverse each bit of r/m8
* NOT r/m8
*/
uint8_t m8;
MEM_BYTE_READ(c, i->modrm.ea, &m8);
INSTR_CALC_AND_SET_FLAGS(8,
c,
m8)
MEM_BYTE_WRITE(c, i->modrm.ea, m8);
}
else
{
/* F6 /2
* Reverse each bit of r/m8
* NOT r/m8
*/
INSTR_CALC_AND_SET_FLAGS(8,c,*c->reg8[i->modrm.rm]);
}
return 0;
}
int32_t instr_group_2_c0_shr(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
/* C0 /5 ib
* Unsigned divide r/m8 by 2, imm8 times
* SHR r/m8,imm8
*/
uint8_t m8;
MEM_BYTE_READ(c, i->modrm.ea, &m8);
INSTR_CALC_AND_SET_FLAGS(8,
c,
m8,
*i->imm8);
MEM_BYTE_WRITE(c, i->modrm.ea, m8);
}
else
{
/* C0 /5 ib
* Unsigned divide r/m8 by 2, imm8 times
* SHR r/m8,imm8
*/
INSTR_CALC_AND_SET_FLAGS(8,
c,
*c->reg8[i->modrm.rm],
*i->imm8);
}
return 0;
}
int32_t instr_group_2_d2_sal(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
/* D2 /4
* Multiply r/m8 by 2, CL times
* SAL r/m8,CL
*/
uint8_t m8;
MEM_BYTE_READ(c, i->modrm.ea, &m8);
INSTR_CALC_AND_SET_FLAGS(8,
c,
m8,
*c->reg8[cl]);
MEM_BYTE_WRITE(c, i->modrm.ea, m8);
}
else
{
/* D2 /4
* Multiply r/m8 by 2, CL times
* SAL r/m8,CL
*/
INSTR_CALC_AND_SET_FLAGS(8,
c,
*c->reg8[i->modrm.rm],
*c->reg8[cl]);
}
return 0;
}
int32_t instr_group_2_c0_rcl(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
/* C0 /2 ib
* Rotate nine bits (CF,r/m8) left imm8 times
* RCL r/m8,imm8
*/
uint8_t m8;
MEM_BYTE_READ(c, i->modrm.ea, &m8);
INSTR_CALC_AND_SET_FLAGS(8,
c,
m8,
*i->imm8);
MEM_BYTE_WRITE(c, i->modrm.ea, m8);
}
else
{
/* C0 /2 ib
* Rotate nine bits (CF,r/m8) left imm8 times
* RCL r/m8,imm8
*/
INSTR_CALC_AND_SET_FLAGS(8,
c,
*c->reg8[i->modrm.rm],
*i->imm8);
}
return 0;
}
int32_t instr_group_3_f6_neg(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
/* F6 /3
* Two's complement negate r/m8
* NEG r/m8
*/
uint8_t m8;
MEM_BYTE_READ(c, i->modrm.ea, &m8);
INSTR_CALC_AND_SET_FLAGS(8,
c,
m8)
MEM_BYTE_WRITE(c, i->modrm.ea, m8);
}
else
{
/* F6 /3
* Two's complement negate r/m8
* NEG r/m8
*/
INSTR_CALC_AND_SET_FLAGS(8,c,*c->reg8[i->modrm.rm]);
}
return 0;
}
int32_t instr_group_2_d0_sar(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
/* D0 /7
* Signed divide* r/m8 by 2, once
* SAR r/m8,1
*/
uint8_t m8;
MEM_BYTE_READ(c, i->modrm.ea, &m8);
INSTR_CALC_AND_SET_FLAGS(8,
c,
m8,
1);
MEM_BYTE_WRITE(c, i->modrm.ea, m8);
}
else
{
/* D0 /7
* Signed divide* r/m8 by 2, once
* SAR r/m8,1
*/
INSTR_CALC_AND_SET_FLAGS(8,
c,
*c->reg8[i->modrm.rm],
1);
}
return 0;
}
int32_t instr_group_2_d2_rcr(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
/* D2 /3
* Rotate nine bits (CF,r/m8) right CL times
* RCR r/m8,CL
*/
uint8_t m8;
MEM_BYTE_READ(c, i->modrm.ea, &m8);
INSTR_CALC_AND_SET_FLAGS(8,
c,
m8,
*c->reg8[cl]);
MEM_BYTE_WRITE(c, i->modrm.ea, m8);
}
else
{
/* D2 /3
* Rotate nine bits (CF,r/m8) right CL times
* RCR r/m8,CL
*/
INSTR_CALC_AND_SET_FLAGS(8,
c,
*c->reg8[i->modrm.rm],
*c->reg8[cl]);
}
return 0;
}
int32_t instr_group_5_ff_inc(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* FF /0
* Increment r/m word by 1
* INC r/m16
*/
uint16_t dst;
MEM_WORD_READ(c, i->modrm.ea, &dst);
INSTR_CALC_AND_SET_FLAGS(16, c, dst)
MEM_WORD_WRITE(c, i->modrm.ea, dst);
}
else
{
/* FF /0
* Increment r/m doubleword by 1
* INC r/m32
*/
uint32_t dst;
MEM_DWORD_READ(c, i->modrm.ea, &dst);
INSTR_CALC_AND_SET_FLAGS(32, c, dst)
MEM_DWORD_WRITE(c, i->modrm.ea, dst);
}
}
else
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* FF /0
* Increment r/m word by 1
* INC r/m16
*/
INSTR_CALC_AND_SET_FLAGS(16, c, *c->reg16[i->modrm.rm])
}
else
{
/* FF /0
* Increment r/m doubleword by 1
* INC r/m32
*/
INSTR_CALC_AND_SET_FLAGS(32, c, c->reg[i->modrm.rm])
}
}
return 0;
}
int32_t instr_inc_4x(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* 40+ rw
* Increment word register by 1
* INC r16
*/
INSTR_CALC_AND_SET_FLAGS(16, c, *c->reg16[i->opc & 7])
}else
{
/* 40+ rd
* Increment doubleword register by 1
* INC r32
*/
INSTR_CALC_AND_SET_FLAGS(32, c, c->reg[i->opc & 7])
}
return 0;
}
int32_t instr_group_4_fe_inc(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
/* FE /0
* INC r/m8
* Increment r/m byte by 1
*/
if ( i->modrm.mod != 3 )
{
uint8_t dst;
MEM_BYTE_READ(c, i->modrm.ea, &dst);
INSTR_CALC_AND_SET_FLAGS(8, c, dst)
MEM_BYTE_WRITE(c, i->modrm.ea, dst);
}
else
{
INSTR_CALC_AND_SET_FLAGS(8, c, *c->reg8[i->modrm.rm])
}
return 0;
}
int32_t instr_group_2_d3_shr(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* D3 /5
* Unsigned divide r/m16 by 2, CL times
* SHR r/m16,CL
*/
uint16_t m16;
MEM_WORD_READ(c, i->modrm.ea, &m16);
INSTR_CALC_AND_SET_FLAGS(16,
c,
m16,
*c->reg8[cl]);
MEM_WORD_WRITE(c, i->modrm.ea, m16);
}
else
{
/* D3 /5
* Unsigned divide r/m32 by 2, CL times
* SHR r/m32,CL
*/
uint32_t m32;
MEM_DWORD_READ(c, i->modrm.ea, &m32);
INSTR_CALC_AND_SET_FLAGS(32,
c,
m32,
*c->reg8[cl]);
MEM_DWORD_WRITE(c, i->modrm.ea, m32);
}
}
else
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* D3 /5
* Unsigned divide r/m16 by 2, CL times
* SHR r/m16,CL
*/
INSTR_CALC_AND_SET_FLAGS(16,
c,
*c->reg16[i->modrm.rm],
*c->reg8[cl]);
}
else
{
/* D3 /5
* Unsigned divide r/m32 by 2, CL times
* SHR r/m32,CL
*/
INSTR_CALC_AND_SET_FLAGS(32,
c,
c->reg[i->modrm.rm],
*c->reg8[cl]);
}
}
return 0;
}
int32_t instr_group_3_f7_not(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* F7 /2
* Reverse each bit of r/m16
* NOT r/m16
*/
uint16_t m16;
MEM_WORD_READ(c, i->modrm.ea, &m16);
INSTR_CALC_AND_SET_FLAGS(16,
c,
m16)
MEM_WORD_WRITE(c, i->modrm.ea, m16);
}
else
{
/* F7 /2
* Reverse each bit of r/m32
* NOT r/m32
*/
uint32_t m32;
MEM_DWORD_READ(c, i->modrm.ea, &m32);
INSTR_CALC_AND_SET_FLAGS(32,
c,
m32)
MEM_DWORD_WRITE(c, i->modrm.ea, m32);
}
}
else
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* F7 /2
* Reverse each bit of r/m16
* NOT r/m16
*/
INSTR_CALC_AND_SET_FLAGS(16,
c,
*c->reg16[i->modrm.rm])
}
else
{
/* F7 /2
* Reverse each bit of r/m32
* NOT r/m32
*/
INSTR_CALC_AND_SET_FLAGS(32,
c,
c->reg[i->modrm.rm])
}
}
return 0;
}
int32_t instr_group_2_d3_rcl(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* D3 /2
* Rotate 17 bits (CF,r/m16) left CL times
* RCL r/m16,CL
*/
uint16_t m16;
MEM_WORD_READ(c, i->modrm.ea, &m16);
INSTR_CALC_AND_SET_FLAGS(16,
c,
m16,
*c->reg8[cl]);
MEM_WORD_WRITE(c, i->modrm.ea, m16);
}
else
{
/* D3 /2
* Rotate 33 bits (CF,r/m32) left CL times
* RCL r/m32,CL
*/
uint32_t m32;
MEM_DWORD_READ(c, i->modrm.ea, &m32);
INSTR_CALC_AND_SET_FLAGS(32,
c,
m32,
*c->reg8[cl]);
MEM_DWORD_WRITE(c, i->modrm.ea, m32);
}
}
else
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* D3 /2
* Rotate 17 bits (CF,r/m16) left CL times
* RCL r/m16,CL
*/
INSTR_CALC_AND_SET_FLAGS(16,
c,
*c->reg16[i->modrm.rm],
*c->reg8[cl]);
}
else
{
/* D3 /2
* Rotate 33 bits (CF,r/m32) left CL times
* RCL r/m32,CL
*/
INSTR_CALC_AND_SET_FLAGS(32,
c,
c->reg[i->modrm.rm],
*c->reg8[cl]);
}
}
return 0;
}
int32_t instr_group_2_d1_sal(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* D1 /4
* Multiply r/m16 by 2, once
* SAL r/m16,1
*/
uint16_t m16;
MEM_WORD_READ(c, i->modrm.ea, &m16);
INSTR_CALC_AND_SET_FLAGS(16,
c,
m16,
1);
MEM_WORD_WRITE(c, i->modrm.ea, m16);
}
else
{
/* D1 /4
* Multiply r/m32 by 2, once
* SAL r/m32,1
*/
uint32_t m32;
MEM_DWORD_READ(c, i->modrm.ea, &m32);
INSTR_CALC_AND_SET_FLAGS(32,
c,
m32,
1);
MEM_DWORD_WRITE(c, i->modrm.ea, m32);
}
}
else
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* D1 /4
* Multiply r/m16 by 2, once
* SAL r/m16,1
*/
INSTR_CALC_AND_SET_FLAGS(16,
c,
*c->reg16[i->modrm.rm],
1);
}
else
{
/* D1 /4
* Multiply r/m32 by 2, once
* SAL r/m32,1
*/
INSTR_CALC_AND_SET_FLAGS(32,
c,
c->reg[i->modrm.rm],
1);
}
}
return 0;
}
int32_t instr_group_2_c1_sar(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* C1 /7 ib
* Signed divide* r/m16 by 2, imm8 times
* SAR r/m16,imm8
*/
uint16_t m16;
MEM_WORD_READ(c, i->modrm.ea, &m16);
INSTR_CALC_AND_SET_FLAGS(16,
c,
m16,
*i->imm8);
MEM_WORD_WRITE(c, i->modrm.ea, m16);
}
else
{
/* C1 /7 ib
* Signed divide* r/m32 by 2, imm8 times
* SAR r/m32,imm8
*/
uint32_t m32;
MEM_DWORD_READ(c, i->modrm.ea, &m32);
INSTR_CALC_AND_SET_FLAGS(32,
c,
m32,
*i->imm8);
MEM_DWORD_WRITE(c, i->modrm.ea, m32);
}
}
else
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* C1 /7 ib
* Signed divide* r/m16 by 2, imm8 times
* SAR r/m16,imm8
*/
INSTR_CALC_AND_SET_FLAGS(16,
c,
*c->reg16[i->modrm.rm],
*i->imm8);
}
else
{
/* C1 /7 ib
* Signed divide* r/m32 by 2, imm8 times
* SAR r/m32,imm8
*/
INSTR_CALC_AND_SET_FLAGS(32,
c,
c->reg[i->modrm.rm],
*i->imm8);
}
}
return 0;
}
int32_t instr_group_2_d1_rcr(struct emu_cpu *c, struct emu_cpu_instruction *i)
{
if ( i->modrm.mod != 3 )
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* D1 /3
* Rotate 17 bits (CF,r/m16) right once
* RCR r/m16,1
*/
uint16_t m16;
MEM_WORD_READ(c, i->modrm.ea, &m16);
INSTR_CALC_AND_SET_FLAGS(16,
c,
m16,
1);
MEM_WORD_WRITE(c, i->modrm.ea, m16);
}
else
{
/* D1 /3
* Rotate 33 bits (CF,r/m32) right once
* RCR r/m32,1
*/
uint32_t m32;
MEM_DWORD_READ(c, i->modrm.ea, &m32);
INSTR_CALC_AND_SET_FLAGS(32,
c,
m32,
1);
MEM_DWORD_WRITE(c, i->modrm.ea, m32);
}
}
else
{
if ( i->prefixes & PREFIX_OPSIZE )
{
/* D1 /3
* Rotate 17 bits (CF,r/m16) right once
* RCR r/m16,1
*/
INSTR_CALC_AND_SET_FLAGS(16,
c,
*c->reg16[i->modrm.rm],
1);
}
else
{
/* D1 /3
* Rotate 33 bits (CF,r/m32) right once
* RCR r/m32,1
*/
INSTR_CALC_AND_SET_FLAGS(32,
c,
c->reg[i->modrm.rm],
1);
}
}
return 0;
}
