int32 ptrio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 016) /* only fnc 0,1 */
return IOBADFNC (dat);
ptr_motion = fnc ^ 1;
if (fnc) /* fnc 1? stop */
sim_cancel (&ptr_unit);
else sim_activate (&ptr_unit, ptr_unit.wait); /* fnc 0? start */
break;
case ioSKS: /* SKS */
if (fnc & 013) /* only fnc 0,4 */
return IOBADFNC (dat);
if (((fnc == 000) && TST_INT (INT_PTR)) || /* fnc 0? skip rdy */
((fnc == 004) && !TST_INTREQ (INT_PTR))) /* fnc 4? skip !int */
return IOSKIP (dat);
break;
case ioINA: /* INA */
if (fnc) /* only fnc 0 */
return IOBADFNC (dat);
if (TST_INT (INT_PTR)) { /* ready? */
CLR_INT (INT_PTR); /* clear ready */
if (ptr_motion) /* if motion, restart */
sim_activate (&ptr_unit, ptr_unit.wait);
return IOSKIP (ptr_unit.buf | dat); /* ret buf, skip */
}
break;
} /* end case op */
return dat;
}
int32 clkio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 015) /* only fnc 0,2 */
return IOBADFNC (dat);
CLR_INT (INT_CLK); /* reset ready */
if (fnc) /* fnc = 2? stop */
sim_cancel (&clk_unit);
else { /* fnc = 0? */
if (!sim_is_active (&clk_unit))
sim_activate (&clk_unit, /* activate */
sim_rtc_init (clk_unit.wait)); /* init calibr */
}
break;
case ioSKS: /* SKS */
if (fnc == 000) { /* clock skip !int */
if (!TST_INTREQ (INT_CLK))
return IOSKIP (dat);
}
else if ((fnc & 007) == 002) { /* mem parity? */
if (((fnc == 002) && !TST_INT (INT_MPE)) ||
((fnc == 012) && TST_INT (INT_MPE)))
return IOSKIP (dat);
}
else return IOBADFNC (dat); /* invalid fnc */
break;
case ioOTA: /* OTA */
if (fnc == 000) /* SMK */
dev_enb = dat;
else if (fnc == 010) { /* OTK */
C = (dat >> 15) & 1; /* set C */
if (cpu_unit.flags & UNIT_HSA) /* HSA included? */
dp = (dat >> 14) & 1; /* set dp */
if (cpu_unit.flags & UNIT_EXT) { /* ext opt? */
if (dat & 020000) { /* ext set? */
ext = 1; /* yes, set */
extoff_pending = 0;
}
else extoff_pending = 1; /* no, clr later */
}
sc = dat & 037; /* set sc */
}
else return IOBADFNC (dat);
int32 ptpio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 016) /* only fnc 0,1 */
return IOBADFNC (dat);
if (fnc) { /* fnc 1? pwr off */
CLR_INT (INT_PTP); /* not ready */
ptp_power = 0; /* turn off power */
sim_cancel (&ptp_unit); /* stop punch */
}
else if (ptp_power == 0) /* fnc 0? start */
sim_activate (&ptp_unit, ptp_ptime);
break;
case ioSKS: /* SKS */
if ((fnc & 012) || (fnc == 005)) /* only 0, 1, 4 */
return IOBADFNC (dat);
if (((fnc == 000) && TST_INT (INT_PTP)) || /* fnc 0? skip rdy */
((fnc == 001) && /* fnc 1? skip ptp on */
(ptp_power || sim_is_active (&ptp_unit))) ||
((fnc == 004) && !TST_INTREQ (INT_PTP))) /* fnc 4? skip !int */
return IOSKIP (dat);
break;
case ioOTA: /* OTA */
if (fnc) /* only fnc 0 */
return IOBADFNC (dat);
if (TST_INT (INT_PTP)) { /* if ptp ready */
CLR_INT (INT_PTP); /* clear ready */
ptp_unit.buf = dat & 0377; /* store byte */
sim_activate (&ptp_unit, ptp_unit.wait);
return IOSKIP (dat); /* skip return */
}
break;
}
return dat;
}
int32 dpio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
int32 ch = dp_dib.chan - 1; /* DMA/DMC chan */
int32 u;
UNIT *uptr;
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
switch (fnc) { /* case on function */
case FNC_SK0: case FNC_SEEK: case FNC_RCA: /* data transfer */
case FNC_UNL: case FNC_FMT: case FNC_RW:
dp_go (fnc); /* if !busy, start */
break;
case FNC_STOP: /* stop transfer */
if (dp_xip) { /* transfer in prog? */
uptr = dp_dev.units + (dp_xip & XIP_UMSK); /* get unit */
sim_cancel (uptr); /* stop operation */
if (dp_xip & (XIP_WRT|XIP_FMT)) /* write or format? */
dp_wrdone (uptr, /* write track */
((dp_xip & XIP_FMT) && /* check fmt state */
(uptr->FNC != (FNC_FMT|FNC_2ND)))?
STA_DTRER: 0);
else dp_done (1, dp_csum? STA_CSMER: 0);/* no, just clr busy */
dp_xip = 0; /* clear flag */
}
dp_otas = OTA_NOP; /* clear state */
dp_sta = dp_sta & ~STA_BUSY; /* clear busy */
break;
case FNC_RDS: /* read status */
if (dp_sta & STA_BUSY) /* ignore if busy */
return dat;
dp_sta = (dp_sta | STA_RDY) & ~(STA_MBZ | STA_ANYER);
if (dp_sta & STA_ALLERR) dp_sta = dp_sta | STA_ANYER;
dp_buf = dp_sta;
if (dp_dma && Q_DMA (ch)) /* DMA? set chan req */
SET_CH_REQ (ch);
break;
case FNC_DMA: /* set DMA/DMC */
dp_dma = 1;
break;
case FNC_IOBUS: /* set IO bus */
dp_dma = 0;
break;
case FNC_AKI: /* ack intr */
CLR_INT (INT_DP);
break;
default: /* undefined */
return IOBADFNC (dat);
}
break;
case ioINA: /* INA */
if (fnc) /* fnc 0 only */
return IOBADFNC (dat);
if (dp_sta & STA_RDY) { /* ready? */
dp_sta = dp_sta & ~STA_RDY; /* clear ready */
return IOSKIP (dat | dp_buf); /* ret buf, skip */
}
break;
case ioOTA: /* OTA */
if (fnc) /* fnc 0 only */
return IOBADFNC (dat);
if (dp_sta & STA_RDY) { /* ready? */
dp_sta = dp_sta & ~STA_RDY; /* clear ready */
dp_buf = dat; /* store buf */
if (dp_otas == OTA_CW1) /* expecting CW1? */
dp_go1 (dat);
else if (dp_otas == OTA_CW2) /* expecting CW2? */
dp_go2 (dat);
return IOSKIP (dat);
}
break;
case ioSKS: /* SKS */
u = 7; /* assume unit 7 */
switch (fnc) {
case 000: /* ready */
if (dp_sta & STA_RDY)
return IOSKIP (dat);
break;
case 001: /* !interrupting */
if (!TST_INTREQ (INT_DP))
return IOSKIP (dat);
break;
case 002: /* operational */
if (!(dp_sta & (STA_BUSY | STA_ALLERR)))
return IOSKIP (dat);
break;
case 003: /* !error */
if (!(dp_sta & STA_ALLERR))
return IOSKIP (dat);
break;
case 004: /* !busy */
if (!(dp_sta & STA_BUSY))
return IOSKIP (dat);
break;
case 011: case 012: case 013: /* !not seeking 0-6 */
case 014: case 015: case 016: case 017:
u = fnc - 011;
case 007: /* !not seeking 7 */
if (!sim_is_active (&dp_unit[u]) || /* quiescent? */
(dp_unit[u].FNC != (FNC_SEEK | FNC_2ND)))
return IOSKIP (dat); /* seeking sets late */
break;
}
break;
case ioEND: /* end of range */
dp_eor = 1; /* transfer done */
break;
}
return dat;
}
// Common I/O simulation routine ...
int32 hi_io (uint16 host, int32 inst, int32 fnc, int32 dat, int32 dev)
{
// This routine is invoked by the CPU module whenever the code executes any
// I/O instruction (OCP, SKS, INA or OTA) with one of our modem's device
// address.
// OCP (output control pulse) initiates various modem operations ...
if (inst == ioOCP) {
switch (fnc) {
case 000:
// HnROUT - start regular host output ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "start regular output (PC=%06o)\n", PC-1);
return dat;
case 001:
// HnIN - start host input ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "start input (PC=%06o)\n", PC-1);
return dat;
case 002:
// HnFOUT - start final host output ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "start final output (PC=%06o)\n", PC-1);
return dat;
case 003:
// HnXP - cross patch ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "enable cross patch (PC=%06o)\n", PC-1);
return dat;
case 004:
// HnUNXP - un-cross patch ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "disable cross patch (PC=%06o)\n", PC-1);
return dat;
case 005:
// HnENAB - enable ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "enable host (PC=%06o)\n", PC-1);
return dat;
}
// SKS (skip) tests various modem conditions ...
} else if (inst == ioSKS) {
switch (fnc) {
case 000:
// HnERR - skip on host error ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "skip on error (PC=%06o %s)\n", PC-1, "NOSKIP");
return dat;
case 001:
// HnRDY - skip on host ready ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "skip on ready (PC=%06o %s)\n", PC-1, "NOSKIP");
return dat;
case 002:
// HnEOM - skip on end of message ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "skip on end of message (PC=%06o %s)\n", PC-1, "NOSKIP");
return dat;
case 005:
// HnFULL - skip on host buffer full ...
sim_debug(IMP_DBG_IOT, PDEVICE(host), "skip on buffer full (PC=%06o %s)\n", PC-1, "NOSKIP");
return dat;
}
}
// Anything else is an error...
sim_debug(IMP_DBG_WARN, PDEVICE(host), "UNIMPLEMENTED I/O (PC=%06o, instruction=%o, function=%02o)\n", PC-1, inst, fnc);
return IOBADFNC(dat);
}
int32 ttyio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 016) /* only fnc 0,1 */
return IOBADFNC (dat);
if (fnc && (tty_mode == 0)) { /* input to output? */
if (!sim_is_active (&tty_unit[TTO])) /* set ready */
SET_INT (INT_TTY);
tty_mode = 1; /* mode is output */
}
else if ((fnc == 0) && tty_mode) { /* output to input? */
CLR_INT (INT_TTY); /* clear ready */
tty_mode = 0; /* mode is input */
}
break;
case ioSKS: /* SKS */
if (fnc & 012) /* fnc 0,1,4,5 */
return IOBADFNC (dat);
if (((fnc == 000) && TST_INT (INT_TTY)) || /* fnc 0? skip rdy */
((fnc == 001) && /* fnc 1? skip !busy */
(!tty_mode || !sim_is_active (&tty_unit[TTO]))) ||
((fnc == 004) && !TST_INTREQ (INT_TTY)) || /* fnc 4? skip !int */
((fnc == 005) && (tty_mode || /* fnc 5? skip !xoff */
((tty_buf & 0177) != XOFF)))) /* input & XOFF char */
return IOSKIP (dat);
break;
case ioINA: /* INA */
if (fnc & 005) /* only 0,2 */
return IOBADFNC (dat);
if (TST_INT (INT_TTY)) { /* ready? */
if (tty_mode == 0) /* inp? clear rdy */
CLR_INT (INT_TTY);
return IOSKIP (dat |
(tty_buf & ((fnc & 002)? 077: 0377)));
}
break;
case ioOTA:
if (fnc & 015) /* only 0,2 */
return IOBADFNC (dat);
if (TST_INT (INT_TTY)) { /* ready? */
tty_buf = dat & 0377; /* store char */
if (fnc & 002) { /* binary mode? */
tty_buf = tty_buf | 0100; /* set ch 7 */
if (tty_buf & 040)
tty_buf = tty_buf & 0277;
}
if (tty_mode) {
sim_activate (&tty_unit[TTO], tty_unit[TTO].wait);
CLR_INT (INT_TTY);
}
return IOSKIP (dat);
}
break;
} /* end case op */
return dat;
}
