_mqx_int _bsp_aud_mclk_io_init(void)
{
IOMUXC_RGPIO(40) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT = IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT_DAISY(2);
return MQX_OK;
}
/*FUNCTION*****************************************************************
*
* Function Name : lwgpio_init
* Returned Value : TRUE if succesfull, FALSE otherwise
* Comments :
* Decodes ID to HW specific struct and then performs pin initialization
*
*END*********************************************************************/
boolean lwgpio_init
(
/* Pointer to LWGPIO internal structure to be filled in */
LWGPIO_STRUCT_PTR handle,
/* Pin ID, bitmask integer value */
LWGPIO_PIN_ID id,
/* Direction to be set within initialization */
LWGPIO_DIR dir,
/* Value to be set within initialization */
LWGPIO_VALUE value
)
{ /* Body */
uint_32 port_idx, pin_idx, temp, ta, tb;
PORT_MemMapPtr port_ptr;
port_idx = LWGPIO_PORT_FROM_ID(id);
pin_idx = LWGPIO_PIN_FROM_ID(id);
handle->flags = id;
handle->pcr_reg = (uint_32 *) pcr_reg_arr[port_idx] + pin_idx;
handle->gpio_ptr = gpio_ptr_arr[port_idx];
handle->pinmask = 1 << pin_idx;
handle->iomuxc_reg = (uint_32 *)&IOMUXC_RGPIO(((port_idx << 5) + pin_idx));
/* Set value prior to set to output */
if (value != LWGPIO_VALUE_NOCHANGE) {
/* Note: there is no check for values not defined as LWGPIO_VALUE enum */
lwgpio_set_value(handle, value);
}
if (dir != LWGPIO_DIR_NOCHANGE) {
/* Note: there is no check for values not defined as LWGPIO_DIR enum */
lwgpio_set_direction(handle, dir);
}
return TRUE;
}
void _bsp_esai_io_init(void)
{
_bsp_esai_clocks_init();
IOMUXC_RGPIO(54) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_RGPIO(55) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_RGPIO(56) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;
IOMUXC_RGPIO(57) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;
IOMUXC_RGPIO(58) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;
IOMUXC_RGPIO(59) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;
IOMUXC_RGPIO(60) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_RGPIO(61) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_MASK;
IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_MASK;
IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_MASK;
IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_MASK;
IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_MASK;
//Configure the DSPI0 to the mode of slave
IOMUXC_RGPIO(41) =
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(1);
IOMUXC_RGPIO(42) =
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(1);
IOMUXC_RGPIO(43) =
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(1);
IOMUXC_RGPIO(44) =
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(1);
_bsp_aud_temp_codec_hw_init();
}
