// Uses value in IR to determine course of action
// Returns false if errors
bool interpreter() {
bool success = true;
//While no error flag and no timer interrupt
while (success && timer_interrupt < QUANTUM) {
machine.IR = main_memory[MMU(machine.PC)];
machine.PC++; // Increment Program Counter
unsigned short int op = getOpcode(machine.IR);
switch (op) {
case 0: success = LOD(); break;
case 1: success = STO(); break;
case 2: success = ADD(); break;
case 3: success = SUB(); break;
case 4: success = ADR(); break;
case 5: success = SUR(); break;
case 6: success = AND(); break;
case 7: success = IOR(); break;
case 8: success = NOT(); break;
case 9: success = JMP(); break;
case 10: success = JEQ(); break;
case 11: success = JGT(); break;
case 12: success = JLT(); break;
case 13: success = CMP(); break;
case 14: success = CLR(); break;
case 15: return HLT(); break; //Quit early on HLT
default: success = false; break;
}
usleep(1000000); // Sleep 1 second to allow easier instruction tracing
(*sysclock)++;
timer_interrupt++;
}
timer_interrupt = 0;
return success;
}
void dce_dpm_on(struct output *o)
{
void *sysname=(void*)udev_device_get_sysname(o->d);
ul req=IOR('d',SI_DCE_DP_DPM,o->blk_idx);
l r=ioctl(o->fd,req,&o->blk_idx);
if(ISERR(r)) PERR("output:%s:dce:unable to swich dpm to on\n",sysname);
else LOG("output:%s:dce:dpm on successfully\n",sysname);
}
void dce_double_frame_buffer_free(struct output *o)
{
void *sysname=(void*)udev_device_get_sysname(o->d);
ul req=IOR('d',SI_MEM_FREE,o->fb.gpu_addr);
l r=ioctl(o->fd,req,&o->fb.gpu_addr);
if(ISERR(r))
PERR("output:%s:dce:unable to free frame buffer memory (LEAK!)\n",sysname);
else LOG("output:%s:dce:double frame buffer freed successfully\n",sysname);
}
s8 dce_info_get(s32 output_name)
{
struct output *o=®istry[output_name].output;
ul req=IOR('d',SI_DCE_DPS_INFO,o->dce_info);
l r=ioctl(o->fd,req,&o->dce_info);
if(ISERR(r)){
DCE_ERR("unable to get info\n");
return LWL_ERR;
}
DCE_LOG("got information from the driving hardware\n");
return LWL_OK;
}
void
smdk2800_io_init(void)
{
unsigned int hclk;
unsigned int pclk;
unsigned int tmdat;
#define O PCON_OUTPUT
#define I PCON_INPUT
#define A PCON_ALTFUN
#define _ 0
#define _C(b7,b6,b5,b4,b3,b2,b1,b0) \
((b7<<14)|(b6<<12)|(b5<<10)|(b4<<8)|(b3<<6)|(b2<<4)|(b1<<2)|(b0<<0))
/* GPIO port */
IOW(S3C2800_GPIO_BASE+GPIO_PCONA, _C(O,O,A,A,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPA, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_PCONB, _C(I,O,A,A,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PCONC, _C(_,_,_,_,O,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPC, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_PCOND, _C(A,A,A,A,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPD, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_PCONE, _C(O,O,O,O,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPE, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_PCONF, _C(A,A,A,A,A,A,A,A));
IOW(S3C2800_GPIO_BASE+GPIO_PUPF, 0xff);
IOW(S3C2800_GPIO_BASE+GPIO_EXTINTR, EXTINTR_INIT);
#undef O
#undef I
#undef A
#undef _
#undef _C
/* Get clock value */
if(IOR(S3C2800_CLKMAN_BASE+CLKMAN_CLKCON) & CLKCON_HCLK)
hclk = FCLK / 2;
else
hclk = FCLK;
if(IOR(S3C2800_CLKMAN_BASE+CLKMAN_CLKCON) & CLKCON_PCLK)
pclk = hclk / 2;
else
pclk = hclk;
/* Timer */
if((pclk/F_1MHZ) < 1)
tmdat = 1<<16;
else
tmdat = (pclk/F_1MHZ)<<16;
#define TMDAT_INIT 0xf424
IOW(S3C2800_TIMER0_BASE+TIMER_TMDAT, (tmdat | TMDAT_INIT));
IOW(S3C2800_TIMER1_BASE+TIMER_TMDAT, (tmdat | TMDAT_INIT));
IOW(S3C2800_TIMER2_BASE+TIMER_TMDAT, (tmdat | TMDAT_INIT));
IOW(S3C2800_TIMER0_BASE+TIMER_TMCON, TMCON_MUX_DIV32 | TMCON_INTENA | TMCON_ENABLE);
IOW(S3C2800_TIMER1_BASE+TIMER_TMCON, TMCON_MUX_DIV16 | TMCON_INTENA | TMCON_ENABLE);
IOW(S3C2800_TIMER2_BASE+TIMER_TMCON, TMCON_MUX_DIV8 | TMCON_INTENA | TMCON_ENABLE);
/* Interrupt controller */
IOW(S3C2800_INTCTL_BASE+INTCTL_INTMOD, 0);
IOW(S3C2800_INTCTL_BASE+INTCTL_INTMSK, 0);
/* Initial complete */
SETLED(0x0); /* All LEDs on (o o o) */
}
