/* check if Tandy DAC is still playing */
static bool Tandy_TransferInProgress(void) {
if (real_readw(0x40,0xd0)) return true; /* not yet done */
if (real_readb(0x40,0xd4)==0xff) return false; /* still in init-state */
Bit8u tandy_dma = 1;
if (tandy_sb.port) tandy_dma = tandy_sb.dma;
else if (tandy_dac.port) tandy_dma = tandy_dac.dma;
IO_Write(0x0c,0x00);
Bit16u datalen=(Bit8u)(IO_ReadB(tandy_dma*2+1)&0xff);
datalen|=(IO_ReadB(tandy_dma*2+1)<<8);
if (datalen==0xffff) return false; /* no DMA transfer */
else if ((datalen<0x10) && (real_readb(0x40,0xd4)==0x0f) && (real_readw(0x40,0xd2)==0x1c)) {
/* stop already requested */
return false;
}
return true;
}
bool INT10_VideoState_Restore(Bitu state,RealPt buffer) {
Bitu ct;
if ((state&7)==0) return false;
Bit16u base_seg=RealSeg(buffer);
Bit16u base_dest;
if (state&1) {
base_dest=real_readw(base_seg,RealOff(buffer));
Bit16u crt_reg=real_readw(base_seg,base_dest+0x40);
// reprogram for full access to plane latches
IO_WriteW(0x3c4,0x0704);
IO_WriteW(0x3ce,0x0406);
IO_WriteW(0x3ce,0x0005);
IO_WriteW(0x3c4,0x0002);
mem_writeb(0xaffff,real_readb(base_seg,base_dest+0x42));
IO_WriteW(0x3c4,0x0102);
mem_writeb(0xaffff,real_readb(base_seg,base_dest+0x43));
IO_WriteW(0x3c4,0x0202);
mem_writeb(0xaffff,real_readb(base_seg,base_dest+0x44));
IO_WriteW(0x3c4,0x0402);
mem_writeb(0xaffff,real_readb(base_seg,base_dest+0x45));
IO_WriteW(0x3c4,0x0f02);
mem_readb(0xaffff);
IO_WriteW(0x3c4,0x0100);
// sequencer
for (ct=1; ct<5; ct++) {
IO_WriteW(0x3c4,ct+(real_readb(base_seg,base_dest+0x04+ct)<<8));
}
IO_WriteB(0x3c2,real_readb(base_seg,base_dest+0x09));
IO_WriteW(0x3c4,0x0300);
IO_WriteW(crt_reg,0x0011);
// crt controller
for (ct=0; ct<0x19; ct++) {
IO_WriteW(crt_reg,ct+(real_readb(base_seg,base_dest+0x0a+ct)<<8));
}
IO_ReadB(crt_reg+6);
// attr registers
for (ct=0; ct<4; ct++) {
IO_WriteB(0x3c0,0x10+ct);
IO_WriteB(0x3c0,real_readb(base_seg,base_dest+0x33+ct));
}
// graphics registers
for (ct=0; ct<9; ct++) {
IO_WriteW(0x3ce,ct+(real_readb(base_seg,base_dest+0x37+ct)<<8));
}
IO_WriteB(crt_reg+6,real_readb(base_seg,base_dest+0x04));
IO_ReadB(crt_reg+6);
// attr registers
for (ct=0; ct<0x10; ct++) {
IO_WriteB(0x3c0,ct);
IO_WriteB(0x3c0,real_readb(base_seg,base_dest+0x23+ct));
}
IO_WriteB(0x3c4,real_readb(base_seg,base_dest+0x00));
IO_WriteB(0x3d4,real_readb(base_seg,base_dest+0x01));
IO_WriteB(0x3ce,real_readb(base_seg,base_dest+0x02));
IO_ReadB(crt_reg+6);
IO_WriteB(0x3c0,real_readb(base_seg,base_dest+0x03));
}
if (state&2) {
base_dest=real_readw(base_seg,RealOff(buffer)+2);
mem_writeb(0x410,(mem_readb(0x410)&0xcf) | real_readb(base_seg,base_dest+0x00));
for (ct=0; ct<0x1e; ct++) {
mem_writeb(0x449+ct,real_readb(base_seg,base_dest+0x01+ct));
}
for (ct=0; ct<0x07; ct++) {
mem_writeb(0x484+ct,real_readb(base_seg,base_dest+0x1f+ct));
}
mem_writed(0x48a,real_readd(base_seg,base_dest+0x26));
mem_writed(0x14,real_readd(base_seg,base_dest+0x2a)); // int 5
mem_writed(0x74,real_readd(base_seg,base_dest+0x2e)); // int 1d
mem_writed(0x7c,real_readd(base_seg,base_dest+0x32)); // int 1f
mem_writed(0x10c,real_readd(base_seg,base_dest+0x36)); // int 43
}
if (state&4) {
base_dest=real_readw(base_seg,RealOff(buffer)+4);
Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
IO_WriteB(0x3c6,real_readb(base_seg,base_dest+0x002));
for (ct=0; ct<0x100; ct++) {
IO_WriteB(0x3c8,ct);
IO_WriteB(0x3c9,real_readb(base_seg,base_dest+0x003+ct*3+0));
IO_WriteB(0x3c9,real_readb(base_seg,base_dest+0x003+ct*3+1));
IO_WriteB(0x3c9,real_readb(base_seg,base_dest+0x003+ct*3+2));
}
IO_ReadB(crt_reg+6);
IO_WriteB(0x3c0,0x14);
IO_WriteB(0x3c0,real_readb(base_seg,base_dest+0x303));
Bitu dac_state=real_readb(base_seg,base_dest+0x000);
if (dac_state==0) {
IO_WriteB(0x3c8,real_readb(base_seg,base_dest+0x001));
} else {
IO_WriteB(0x3c7,real_readb(base_seg,base_dest+0x001));
}
}
if ((svgaCard==SVGA_S3Trio) && (state&8)) {
base_dest=real_readw(base_seg,RealOff(buffer)+6);
Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
Bitu seq_idx=IO_ReadB(0x3c4);
IO_WriteB(0x3c4,0x08);
// Bitu seq_8=IO_ReadB(0x3c5);
IO_ReadB(0x3c5);
// real_writeb(base_seg,base_dest+0x00,IO_ReadB(0x3c5));
IO_WriteB(0x3c5,0x06); // unlock s3-specific registers
// sequencer
for (ct=0; ct<0x13; ct++) {
IO_WriteW(0x3c4,(0x09+ct)+(real_readb(base_seg,base_dest+0x00+ct)<<8));
}
IO_WriteB(0x3c4,seq_idx);
// Bitu crtc_idx=IO_ReadB(0x3d4);
// unlock s3-specific registers
IO_WriteW(crt_reg,0x4838);
IO_WriteW(crt_reg,0xa539);
// crt controller
Bitu ct_dest=0x13;
for (ct=0; ct<0x40; ct++) {
if ((ct==0x4a-0x30) || (ct==0x4b-0x30)) {
IO_WriteB(crt_reg,0x45);
IO_ReadB(crt_reg+1);
IO_WriteB(crt_reg,0x30+ct);
IO_WriteB(crt_reg,real_readb(base_seg,base_dest+(ct_dest++)));
} else {
IO_WriteW(crt_reg,(0x30+ct)+(real_readb(base_seg,base_dest+(ct_dest++))<<8));
}
}
// mmio
/* IO_WriteB(crt_reg,0x40);
Bitu sysval1=IO_ReadB(crt_reg+1);
IO_WriteB(crt_reg+1,sysval|1);
IO_WriteB(crt_reg,0x53);
Bitu sysva2=IO_ReadB(crt_reg+1);
IO_WriteB(crt_reg+1,sysval2|0x10);
real_writew(0xa000,0x8128,0xffff);
IO_WriteB(crt_reg,0x40);
IO_WriteB(crt_reg,sysval1);
IO_WriteB(crt_reg,0x53);
IO_WriteB(crt_reg,sysval2);
IO_WriteB(crt_reg,crtc_idx); */
}
return true;
}
bool INT10_VideoState_Save(Bitu state,RealPt buffer) {
Bitu ct;
if ((state&7)==0) return false;
Bitu base_seg=RealSeg(buffer);
Bitu base_dest=RealOff(buffer)+0x20;
if (state&1) {
real_writew(base_seg,RealOff(buffer),base_dest);
Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
real_writew(base_seg,base_dest+0x40,crt_reg);
real_writeb(base_seg,base_dest+0x00,IO_ReadB(0x3c4));
real_writeb(base_seg,base_dest+0x01,IO_ReadB(0x3d4));
real_writeb(base_seg,base_dest+0x02,IO_ReadB(0x3ce));
IO_ReadB(crt_reg+6);
real_writeb(base_seg,base_dest+0x03,IO_ReadB(0x3c0));
real_writeb(base_seg,base_dest+0x04,IO_ReadB(0x3ca));
// sequencer
for (ct=1; ct<5; ct++) {
IO_WriteB(0x3c4,ct);
real_writeb(base_seg,base_dest+0x04+ct,IO_ReadB(0x3c5));
}
real_writeb(base_seg,base_dest+0x09,IO_ReadB(0x3cc));
// crt controller
for (ct=0; ct<0x19; ct++) {
IO_WriteB(crt_reg,ct);
real_writeb(base_seg,base_dest+0x0a+ct,IO_ReadB(crt_reg+1));
}
// attr registers
for (ct=0; ct<4; ct++) {
IO_ReadB(crt_reg+6);
IO_WriteB(0x3c0,0x10+ct);
real_writeb(base_seg,base_dest+0x33+ct,IO_ReadB(0x3c1));
}
// graphics registers
for (ct=0; ct<9; ct++) {
IO_WriteB(0x3ce,ct);
real_writeb(base_seg,base_dest+0x37+ct,IO_ReadB(0x3cf));
}
// save some registers
IO_WriteB(0x3c4,2);
Bit8u crtc_2=IO_ReadB(0x3c5);
IO_WriteB(0x3c4,4);
Bit8u crtc_4=IO_ReadB(0x3c5);
IO_WriteB(0x3ce,6);
Bit8u gfx_6=IO_ReadB(0x3cf);
IO_WriteB(0x3ce,5);
Bit8u gfx_5=IO_ReadB(0x3cf);
IO_WriteB(0x3ce,4);
Bit8u gfx_4=IO_ReadB(0x3cf);
// reprogram for full access to plane latches
IO_WriteW(0x3c4,0x0f02);
IO_WriteW(0x3c4,0x0704);
IO_WriteW(0x3ce,0x0406);
IO_WriteW(0x3ce,0x0105);
mem_writeb(0xaffff,0);
for (ct=0; ct<4; ct++) {
IO_WriteW(0x3ce,0x0004+ct*0x100);
real_writeb(base_seg,base_dest+0x42+ct,mem_readb(0xaffff));
}
// restore registers
IO_WriteW(0x3ce,0x0004|(gfx_4<<8));
IO_WriteW(0x3ce,0x0005|(gfx_5<<8));
IO_WriteW(0x3ce,0x0006|(gfx_6<<8));
IO_WriteW(0x3c4,0x0004|(crtc_4<<8));
IO_WriteW(0x3c4,0x0002|(crtc_2<<8));
for (ct=0; ct<0x10; ct++) {
IO_ReadB(crt_reg+6);
IO_WriteB(0x3c0,ct);
real_writeb(base_seg,base_dest+0x23+ct,IO_ReadB(0x3c1));
}
IO_WriteB(0x3c0,0x20);
base_dest+=0x46;
}
if (state&2) {
real_writew(base_seg,RealOff(buffer)+2,base_dest);
real_writeb(base_seg,base_dest+0x00,mem_readb(0x410)&0x30);
for (ct=0; ct<0x1e; ct++) {
real_writeb(base_seg,base_dest+0x01+ct,mem_readb(0x449+ct));
}
for (ct=0; ct<0x07; ct++) {
real_writeb(base_seg,base_dest+0x1f+ct,mem_readb(0x484+ct));
}
real_writed(base_seg,base_dest+0x26,mem_readd(0x48a));
real_writed(base_seg,base_dest+0x2a,mem_readd(0x14)); // int 5
real_writed(base_seg,base_dest+0x2e,mem_readd(0x74)); // int 1d
real_writed(base_seg,base_dest+0x32,mem_readd(0x7c)); // int 1f
real_writed(base_seg,base_dest+0x36,mem_readd(0x10c)); // int 43
base_dest+=0x3a;
}
if (state&4) {
real_writew(base_seg,RealOff(buffer)+4,base_dest);
Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
IO_ReadB(crt_reg+6);
IO_WriteB(0x3c0,0x14);
real_writeb(base_seg,base_dest+0x303,IO_ReadB(0x3c1));
Bitu dac_state=IO_ReadB(0x3c7)&1;
Bitu dac_windex=IO_ReadB(0x3c8);
if (dac_state!=0) dac_windex--;
real_writeb(base_seg,base_dest+0x000,dac_state);
real_writeb(base_seg,base_dest+0x001,dac_windex);
real_writeb(base_seg,base_dest+0x002,IO_ReadB(0x3c6));
for (ct=0; ct<0x100; ct++) {
IO_WriteB(0x3c7,ct);
real_writeb(base_seg,base_dest+0x003+ct*3+0,IO_ReadB(0x3c9));
real_writeb(base_seg,base_dest+0x003+ct*3+1,IO_ReadB(0x3c9));
real_writeb(base_seg,base_dest+0x003+ct*3+2,IO_ReadB(0x3c9));
}
IO_ReadB(crt_reg+6);
IO_WriteB(0x3c0,0x20);
base_dest+=0x303;
}
if ((svgaCard==SVGA_S3Trio) && (state&8)) {
real_writew(base_seg,RealOff(buffer)+6,base_dest);
Bit16u crt_reg=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
IO_WriteB(0x3c4,0x08);
// Bitu seq_8=IO_ReadB(0x3c5);
IO_ReadB(0x3c5);
// real_writeb(base_seg,base_dest+0x00,IO_ReadB(0x3c5));
IO_WriteB(0x3c5,0x06); // unlock s3-specific registers
// sequencer
for (ct=0; ct<0x13; ct++) {
IO_WriteB(0x3c4,0x09+ct);
real_writeb(base_seg,base_dest+0x00+ct,IO_ReadB(0x3c5));
}
// unlock s3-specific registers
IO_WriteW(crt_reg,0x4838);
IO_WriteW(crt_reg,0xa539);
// crt controller
Bitu ct_dest=0x13;
for (ct=0; ct<0x40; ct++) {
if ((ct==0x4a-0x30) || (ct==0x4b-0x30)) {
IO_WriteB(crt_reg,0x45);
IO_ReadB(crt_reg+1);
IO_WriteB(crt_reg,0x30+ct);
real_writeb(base_seg,base_dest+(ct_dest++),IO_ReadB(crt_reg+1));
real_writeb(base_seg,base_dest+(ct_dest++),IO_ReadB(crt_reg+1));
real_writeb(base_seg,base_dest+(ct_dest++),IO_ReadB(crt_reg+1));
} else {
IO_WriteB(crt_reg,0x30+ct);
real_writeb(base_seg,base_dest+(ct_dest++),IO_ReadB(crt_reg+1));
}
}
}
return true;
}
void INT10_GenerateVideoParameterTable(void) {
if (!IS_VGA_ARCH) E_Exit("Be sure that all graphics registers are readable!");
Bitu i;
for (i=0; i<4; i++) {
LOG_MSG("// video parameter table for mode %x (cga emulation)",i);
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
}
for (i=4; i<0x0f; i++) {
Bitu ct;
LOG_MSG("// video parameter table for mode %x",i);
if ((i>=8) && (i<0x0d)) {
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
} else {
INT10_SetVideoMode(i);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // bios data",real_readb(0x40,0x4a),real_readb(0x40,0x84),real_readb(0x40,0x85),real_readb(0x40,0x4c),real_readb(0x40,0x4d));
Bitu seq_regs[4];
for (ct=0; ct<4; ct++) {
IO_WriteB(0x3c4,ct+1);
seq_regs[ct]=IO_ReadB(0x3c5);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, // sequencer registers",seq_regs[0],seq_regs[1],seq_regs[2],seq_regs[3]);
LOG_MSG(" 0x%02x, // misc output registers",IO_ReadB(0x3cc));
Bitu crtc_regs[0x19];
Bit16u crt_addr=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
for (ct=0; ct<0x19; ct++) {
IO_WriteB(crt_addr,ct);
crtc_regs[ct]=IO_ReadB(crt_addr+1);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 0-7",
crtc_regs[0x00],crtc_regs[0x01],crtc_regs[0x02],crtc_regs[0x03],
crtc_regs[0x04],crtc_regs[0x05],crtc_regs[0x06],crtc_regs[0x07]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 8-15",
crtc_regs[0x08],crtc_regs[0x09],crtc_regs[0x0a],crtc_regs[0x0b],
crtc_regs[0x0c],crtc_regs[0x0d],crtc_regs[0x0e],crtc_regs[0x0f]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 16-24",
crtc_regs[0x10],crtc_regs[0x11],crtc_regs[0x12],crtc_regs[0x13],
crtc_regs[0x14],crtc_regs[0x15],crtc_regs[0x16],crtc_regs[0x17],crtc_regs[0x18]);
Bitu attr_regs[0x14];
for (ct=0; ct<0x14; ct++) {
IO_ReadB(crt_addr+6);
IO_WriteB(0x3c0,ct);
attr_regs[ct]=IO_ReadB(0x3c1);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 0-7",
attr_regs[0x00],attr_regs[0x01],attr_regs[0x02],attr_regs[0x03],
attr_regs[0x04],attr_regs[0x05],attr_regs[0x06],attr_regs[0x07]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 8-15",
attr_regs[0x08],attr_regs[0x09],attr_regs[0x0a],attr_regs[0x0b],
attr_regs[0x0c],attr_regs[0x0d],attr_regs[0x0e],attr_regs[0x0f]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 16-19",
attr_regs[0x10],attr_regs[0x11],attr_regs[0x12],attr_regs[0x13]);
Bitu gfx_regs[9];
for (ct=0; ct<0x09; ct++) {
IO_WriteB(0x3ce,ct);
gfx_regs[ct]=IO_ReadB(0x3cf);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // graphics registers 0-8",
gfx_regs[0x00],gfx_regs[0x01],gfx_regs[0x02],gfx_regs[0x03],
gfx_regs[0x04],gfx_regs[0x05],gfx_regs[0x06],gfx_regs[0x07],gfx_regs[0x08]);
}
}
for (i=0x0f; i<0x11; i++) {
LOG_MSG("// video parameter table for mode %x (64k graphics memory)",i);
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
}
for (i=0x0f; i<0x11; i++) {
Bitu ct;
INT10_SetVideoMode(i);
LOG_MSG("// video parameter table for mode %x (>64k graphics memory)",i);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // bios data",real_readb(0x40,0x4a),real_readb(0x40,0x84),real_readb(0x40,0x85),real_readb(0x40,0x4c),real_readb(0x40,0x4d));
Bitu seq_regs[4];
for (ct=0; ct<4; ct++) {
IO_WriteB(0x3c4,ct+1);
seq_regs[ct]=IO_ReadB(0x3c5);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, // sequencer registers",seq_regs[0],seq_regs[1],seq_regs[2],seq_regs[3]);
LOG_MSG(" 0x%02x, // misc output registers",IO_ReadB(0x3cc));
Bitu crtc_regs[0x19];
Bit16u crt_addr=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
for (ct=0; ct<0x19; ct++) {
IO_WriteB(crt_addr,ct);
crtc_regs[ct]=IO_ReadB(crt_addr+1);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 0-7",
crtc_regs[0x00],crtc_regs[0x01],crtc_regs[0x02],crtc_regs[0x03],
crtc_regs[0x04],crtc_regs[0x05],crtc_regs[0x06],crtc_regs[0x07]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 8-15",
crtc_regs[0x08],crtc_regs[0x09],crtc_regs[0x0a],crtc_regs[0x0b],
crtc_regs[0x0c],crtc_regs[0x0d],crtc_regs[0x0e],crtc_regs[0x0f]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 16-24",
crtc_regs[0x10],crtc_regs[0x11],crtc_regs[0x12],crtc_regs[0x13],
crtc_regs[0x14],crtc_regs[0x15],crtc_regs[0x16],crtc_regs[0x17],crtc_regs[0x18]);
Bitu attr_regs[0x14];
for (ct=0; ct<0x14; ct++) {
IO_ReadB(crt_addr+6);
IO_WriteB(0x3c0,ct);
attr_regs[ct]=IO_ReadB(0x3c1);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 0-7",
attr_regs[0x00],attr_regs[0x01],attr_regs[0x02],attr_regs[0x03],
attr_regs[0x04],attr_regs[0x05],attr_regs[0x06],attr_regs[0x07]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 8-15",
attr_regs[0x08],attr_regs[0x09],attr_regs[0x0a],attr_regs[0x0b],
attr_regs[0x0c],attr_regs[0x0d],attr_regs[0x0e],attr_regs[0x0f]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 16-19",
attr_regs[0x10],attr_regs[0x11],attr_regs[0x12],attr_regs[0x13]);
Bitu gfx_regs[9];
for (ct=0; ct<0x09; ct++) {
IO_WriteB(0x3ce,ct);
gfx_regs[ct]=IO_ReadB(0x3cf);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // graphics registers 0-8",
gfx_regs[0x00],gfx_regs[0x01],gfx_regs[0x02],gfx_regs[0x03],
gfx_regs[0x04],gfx_regs[0x05],gfx_regs[0x06],gfx_regs[0x07],gfx_regs[0x08]);
}
for (i=0; i<4; i++) {
if (IS_VGA_ARCH) {
LOG_MSG("// video parameter table for mode %x (350 lines)",i);
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
LOG_MSG(" 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,");
} else {
Bitu ct;
INT10_SetVideoMode(i);
LOG_MSG("// video parameter table for mode %x (350 lines)",i);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // bios data",real_readb(0x40,0x4a),real_readb(0x40,0x84),real_readb(0x40,0x85),real_readb(0x40,0x4c),real_readb(0x40,0x4d));
Bitu seq_regs[4];
for (ct=0; ct<4; ct++) {
IO_WriteB(0x3c4,ct+1);
seq_regs[ct]=IO_ReadB(0x3c5);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, // sequencer registers",seq_regs[0],seq_regs[1],seq_regs[2],seq_regs[3]);
LOG_MSG(" 0x%02x, // misc output registers",IO_ReadB(0x3cc));
Bitu crtc_regs[0x19];
Bit16u crt_addr=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
for (ct=0; ct<0x19; ct++) {
IO_WriteB(crt_addr,ct);
crtc_regs[ct]=IO_ReadB(crt_addr+1);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 0-7",
crtc_regs[0x00],crtc_regs[0x01],crtc_regs[0x02],crtc_regs[0x03],
crtc_regs[0x04],crtc_regs[0x05],crtc_regs[0x06],crtc_regs[0x07]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 8-15",
crtc_regs[0x08],crtc_regs[0x09],crtc_regs[0x0a],crtc_regs[0x0b],
crtc_regs[0x0c],crtc_regs[0x0d],crtc_regs[0x0e],crtc_regs[0x0f]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 16-24",
crtc_regs[0x10],crtc_regs[0x11],crtc_regs[0x12],crtc_regs[0x13],
crtc_regs[0x14],crtc_regs[0x15],crtc_regs[0x16],crtc_regs[0x17],crtc_regs[0x18]);
Bitu attr_regs[0x14];
for (ct=0; ct<0x14; ct++) {
IO_ReadB(crt_addr+6);
IO_WriteB(0x3c0,ct);
attr_regs[ct]=IO_ReadB(0x3c1);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 0-7",
attr_regs[0x00],attr_regs[0x01],attr_regs[0x02],attr_regs[0x03],
attr_regs[0x04],attr_regs[0x05],attr_regs[0x06],attr_regs[0x07]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 8-15",
attr_regs[0x08],attr_regs[0x09],attr_regs[0x0a],attr_regs[0x0b],
attr_regs[0x0c],attr_regs[0x0d],attr_regs[0x0e],attr_regs[0x0f]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 16-19",
attr_regs[0x10],attr_regs[0x11],attr_regs[0x12],attr_regs[0x13]);
Bitu gfx_regs[9];
for (ct=0; ct<0x09; ct++) {
IO_WriteB(0x3ce,ct);
gfx_regs[ct]=IO_ReadB(0x3cf);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // graphics registers 0-8",
gfx_regs[0x00],gfx_regs[0x01],gfx_regs[0x02],gfx_regs[0x03],
gfx_regs[0x04],gfx_regs[0x05],gfx_regs[0x06],gfx_regs[0x07],gfx_regs[0x08]);
}
}
if (IS_VGA_ARCH) {
for (i=0x0e; i<0x14; i++) {
Bitu ct=i;
if (i==0x0e) ct=1;
if (i==0x0f) ct=3;
if (i==0x010) ct=7;
INT10_SetVideoMode(ct);
LOG_MSG("// video parameter table for mode %x",i);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // bios data",real_readb(0x40,0x4a),real_readb(0x40,0x84),real_readb(0x40,0x85),real_readb(0x40,0x4c),real_readb(0x40,0x4d));
Bitu seq_regs[4];
for (ct=0; ct<4; ct++) {
IO_WriteB(0x3c4,ct+1);
seq_regs[ct]=IO_ReadB(0x3c5);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, // sequencer registers",seq_regs[0],seq_regs[1],seq_regs[2],seq_regs[3]);
LOG_MSG(" 0x%02x, // misc output registers",IO_ReadB(0x3cc));
Bitu crtc_regs[0x19];
Bit16u crt_addr=real_readw(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS);
for (ct=0; ct<0x19; ct++) {
IO_WriteB(crt_addr,ct);
crtc_regs[ct]=IO_ReadB(crt_addr+1);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 0-7",
crtc_regs[0x00],crtc_regs[0x01],crtc_regs[0x02],crtc_regs[0x03],
crtc_regs[0x04],crtc_regs[0x05],crtc_regs[0x06],crtc_regs[0x07]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 8-15",
crtc_regs[0x08],crtc_regs[0x09],crtc_regs[0x0a],crtc_regs[0x0b],
crtc_regs[0x0c],crtc_regs[0x0d],crtc_regs[0x0e],crtc_regs[0x0f]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // crtc registers 16-24",
crtc_regs[0x10],crtc_regs[0x11],crtc_regs[0x12],crtc_regs[0x13],
crtc_regs[0x14],crtc_regs[0x15],crtc_regs[0x16],crtc_regs[0x17],crtc_regs[0x18]);
Bitu attr_regs[0x14];
for (ct=0; ct<0x14; ct++) {
IO_ReadB(crt_addr+6);
IO_WriteB(0x3c0,ct);
attr_regs[ct]=IO_ReadB(0x3c1);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 0-7",
attr_regs[0x00],attr_regs[0x01],attr_regs[0x02],attr_regs[0x03],
attr_regs[0x04],attr_regs[0x05],attr_regs[0x06],attr_regs[0x07]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 8-15",
attr_regs[0x08],attr_regs[0x09],attr_regs[0x0a],attr_regs[0x0b],
attr_regs[0x0c],attr_regs[0x0d],attr_regs[0x0e],attr_regs[0x0f]);
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, // attr registers 16-19",
attr_regs[0x10],attr_regs[0x11],attr_regs[0x12],attr_regs[0x13]);
Bitu gfx_regs[9];
for (ct=0; ct<0x09; ct++) {
IO_WriteB(0x3ce,ct);
gfx_regs[ct]=IO_ReadB(0x3cf);
}
LOG_MSG(" 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, // graphics registers 0-8",
gfx_regs[0x00],gfx_regs[0x01],gfx_regs[0x02],gfx_regs[0x03],
gfx_regs[0x04],gfx_regs[0x05],gfx_regs[0x06],gfx_regs[0x07],gfx_regs[0x08]);
}
}
INT10_SetVideoMode(3);
E_Exit("done!");
}