/*****************************************************************************
Prototype : HI_MPI_ISP_SetRegister
Description : set isp register, include extent memory.
Input : u32Addr **
u32Value **
Output : None
Return Value :
Process :
Note :
History
1.Date : 2011/1/13
Author : x00100808
Modification : Created function
*****************************************************************************/
HI_S32 HI_MPI_ISP_SetRegister(ISP_DEV IspDev, HI_U32 u32Addr, HI_U32 u32Value)
{
ISP_CHECK_DEV(IspDev);
IO_WRITE32(u32Addr, u32Value);
return HI_SUCCESS;
}
static void phy_auto_negotiation_set(struct am_net_private *np)
{
unsigned int rint;
int s100,full,tmp;
switch(np->phy_Identifier)
{
case PHY_ATHEROS_8032:
rint=mdio_read(np->dev,np->phys[0],0x11);
s100=rint&(1<<14);
full=((rint)&(1<<13));
break;
case PHY_SMSC_8700:
case PHY_SMSC_8720:
default:
rint=mdio_read(np->dev,np->phys[0],31);
s100=rint&(1<<3);
full=((rint>>4)&1);
break;
}
if(full)
{
if (debug > 0)
printk("duplex\n");
//(*ETH_MAC_0_Configuration) |= 1<<11; // program mac
tmp =
IO_READ32(np->base_addr +ETH_MAC_0_Configuration);
tmp |= 1 << 11;
IO_WRITE32(tmp,np->base_addr +ETH_MAC_0_Configuration);
}
else
{
if (debug > 0)
printk("half duplex\n");
//(*ETH_MAC_0_Configuration) &= ~(1<<11) ; // program mac
tmp =
IO_READ32(np->base_addr +ETH_MAC_0_Configuration);
tmp &= ~(1 << 11);
IO_WRITE32(tmp, np->base_addr +ETH_MAC_0_Configuration);
}
mac_PLL_changed(np,s100?100:10);
return;
}
static void mdio_write(struct net_device *dev, int phyid, int reg, int val)
{
#define WR (1<<1)
#define MDCCLK (0x1) << 2 //our 130 MHz
#define BUSY 0x1
struct am_net_private *priv = netdev_priv(dev);
unsigned long busy = 0;
unsigned long reg4;
reg4 = phyid << 11 | reg << 6 | MDCCLK | WR | BUSY;
IO_WRITE32(val, priv->base_addr + ETH_MAC_5_GMII_Data);
do { //waiting the phy is ready to write ...
busy = IO_READ32(priv->base_addr + ETH_MAC_4_GMII_Addr);
} while (busy & 0x1);
IO_WRITE32(reg4, priv->base_addr + ETH_MAC_4_GMII_Addr);
do { //waiting the phy is ready to write ...
busy = IO_READ32(priv->base_addr + ETH_MAC_4_GMII_Addr);
} while (busy & 0x1);
}
void close_8193_NFI(void)
{
/*
1. Power off digital:
RG_NFI_PWR_CTRL[2] = 1 // disable clock
RG_NFI_PWR_CTRL[0] = 1 // en iso
RG_NFI_PWR_RST_B[0] = 0 // en reset
RG_NFI_PWR_CTRL[1] = 0 // turn off power
2. Power off analog
ADDR:0x134C BIT[1] =0
ADDR:0x1354 BIT[20] =0
*/
u32 value = 0;
printf("Close 8193 NFI Digital\n");
//power off digital
value = IO_READ32(0,RG_NFI_PWR_CTRL);
IO_WRITE32(0,RG_NFI_PWR_CTRL,(value | 0x4));
//IO_WRITE32(0,RG_NFI_PWR_CTRL,(value | 0x5));
value = IO_READ32(0,RG_NFI_PWR_CTRL);
IO_WRITE32(0,RG_NFI_PWR_CTRL,(value | 0x1));
value = IO_READ32(0,RG_NFI_PWR_RST_B);
IO_WRITE32(0,RG_NFI_PWR_RST_B,(value & 0xFFFFFFFE));
value = IO_READ32(0,RG_NFI_PWR_CTRL);
IO_WRITE32(0,RG_NFI_PWR_CTRL,(value & 0xFFFFFFFD));
printf("Close 8193 NFI Analog\n");
//power off analog
value = IO_READ32(0,0x134C);
IO_WRITE32(0,0x134C,(value & 0xFFFFFFFD));
//can not close power share power
//value = IO_READ32(0,0x1354);
//IO_WRITE32(0,0x1354,(value & 0xFFEFFFFF));
printf("Close 8193 NFI OK\n");
}
static int mac_PLL_changed(struct am_net_private *np,int clk_mhz)
{
unsigned long tmp;
switch(clk_mhz)
{
case 0://disable clock
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, 1); //disable clk
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, (1 << 0 | 1 << 2 | 1 << 3));
break;
case 10:
if (debug > 0)
printk("10m\n");
//(*ETH_MAC_0_Configuration) &= ~(1<<14); // program mac
tmp =
IO_READ32(np->base_addr +ETH_MAC_0_Configuration);
tmp &= ~(1 << 14);
IO_WRITE32(tmp,np->base_addr +ETH_MAC_0_Configuration);
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, 1);
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, (1 << 1));
PERIPHS_SET_BITS(PREG_ETHERNET_ADDR0, 1);
break;
case 100:
default:
if (debug > 0)
printk("100m\n");
//(*ETH_MAC_0_Configuration) |= 1<<14; // program mac
tmp =
IO_READ32(np->base_addr +ETH_MAC_0_Configuration);
tmp |= 1 << 14;
IO_WRITE32(tmp,np->base_addr +ETH_MAC_0_Configuration);
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, 1);
PERIPHS_SET_BITS(PREG_ETHERNET_ADDR0, (1 << 1));
PERIPHS_SET_BITS(PREG_ETHERNET_ADDR0, 1);
}
udelay(10);
return 0;
}
int mt8193_vopll_en()
{
printf("mt8193_pllgp_en() enter\n");
/* PLL2 setup of 75MHZ. AD_PLLGP_CLK=450MHZ*/
IO_WRITE32(0, 0x44c, 0x1);
// CKGEN_WRITE32(REG_RW_PLL_GPANACFG0, 0xAD300982);
CKGEN_WRITE32(REG_RW_LVDS_ANACFG2, 0x32215000);
CKGEN_WRITE32(REG_RW_LVDS_ANACFG3, 0x410c0);
CKGEN_WRITE32(REG_RW_LVDS_ANACFG4, 0x300);
printf("mt8193_pllgp_en() exit\n");
return 0;
}
static int mdio_read(struct net_device *dev, int phyid, int reg)
{
#define WR (1<<1)
#define MDCCLK (0x1) << 2 //our 130 MHz
#define BUSY 0x1
struct am_net_private *priv = netdev_priv(dev);
unsigned long busy = 0;
unsigned long reg4;
unsigned long val = 0;
reg4 = phyid << 11 | reg << 6 | MDCCLK | BUSY;
/*
do{ //waiting the phy is ready to write ...
busy=IO_READ32(priv->base_addr+ETH_MAC_4_GMII_Addr);
}while(busy&0x1);
*/
IO_WRITE32(reg4, priv->base_addr + ETH_MAC_4_GMII_Addr);
do { //waiting the phy is ready to write ...
busy = IO_READ32(priv->base_addr + ETH_MAC_4_GMII_Addr);
} while (busy & 0x1);
val = IO_READ32(priv->base_addr + ETH_MAC_5_GMII_Data) & 0xffff;
return val;
}
static inline int update_status(struct net_device *dev, unsigned long status,
unsigned long mask)
{
struct am_net_private *np = netdev_priv(dev);
int need_reset = 0;
int need_rx_restart = 0;
int res = 0;
if (status & NOR_INTR_EN) //Normal Interrupts Process
{
if (status & TX_INTR_EN) //Transmit Interrupt Process
{
IO_WRITE32((1 << 0 | 1 << 16),np->base_addr + ETH_DMA_5_Status);
res |= 1;
}
if (status & RX_INTR_EN) //Receive Interrupt Process
{
IO_WRITE32((1 << 6 | 1 << 16),np->base_addr + ETH_DMA_5_Status);
res |= 2;
}
if (status & EARLY_RX_INTR_EN) {
IO_WRITE32((EARLY_RX_INTR_EN | NOR_INTR_EN),np->base_addr + ETH_DMA_5_Status);
}
if (status & TX_BUF_UN_EN) {
IO_WRITE32((1 << 2 | 1 << 16),np->base_addr + ETH_DMA_5_Status);
res |= 1;
//this error will cleard in start tx...
if (debug > 1)
printk(KERN_WARNING "[" DRV_NAME "]" "Tx bufer unenable\n");
}
} else if (status & ANOR_INTR_EN) //Abnormal Interrupts Process
{
if (status & RX_BUF_UN) {
IO_WRITE32((RX_BUF_UN | ANOR_INTR_EN),np->base_addr + ETH_DMA_5_Status);
np->stats.rx_over_errors++;
need_rx_restart++;
res |= 2;
//printk(KERN_WARNING DRV_NAME "Receive Buffer Unavailable\n");
if (debug > 1)
printk(KERN_WARNING "[" DRV_NAME "]" "Rx bufer unenable\n");
}
if (status & RX_STOP_EN) {
IO_WRITE32((RX_STOP_EN | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
need_rx_restart++;
res |= 2;
}
if (status & RX_WATCH_TIMEOUT) {
IO_WRITE32((RX_WATCH_TIMEOUT | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
need_rx_restart++;
}
if (status & FATAL_BUS_ERROR) {
IO_WRITE32((FATAL_BUS_ERROR | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
need_reset++;
printk(KERN_WARNING "[" DRV_NAME "]" "fatal bus error\n");
}
if (status & EARLY_TX_INTR_EN) {
IO_WRITE32((EARLY_TX_INTR_EN | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
}
if (status & TX_STOP_EN) {
IO_WRITE32((TX_STOP_EN | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
res |= 1;
}
if (status & TX_JABBER_TIMEOUT) {
IO_WRITE32((TX_JABBER_TIMEOUT | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
printk(KERN_WARNING "[" DRV_NAME "]" "tx jabber timeout\n");
np->first_tx = 1;
}
if (status & RX_FIFO_OVER) {
IO_WRITE32((RX_FIFO_OVER | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
np->stats.rx_fifo_errors++;
need_rx_restart++;
res |= 2;
printk(KERN_WARNING "[" DRV_NAME "]" "Rx fifo over\n");
}
if (status & TX_UNDERFLOW) {
IO_WRITE32((TX_UNDERFLOW | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
printk(KERN_WARNING "[" DRV_NAME "]" "Tx underflow\n");
np->first_tx = 1;
res |= 1;
}
}
if (need_reset) {
printk(KERN_WARNING DRV_NAME "system reset\n");
free_ringdesc(dev);
ethernet_reset(dev);
} else if (need_rx_restart) {
IO_WRITE32(1, np->base_addr + ETH_DMA_2_Re_Poll_Demand);
}
return res;
}
u32 mt8193_io_agent_test(void)
{
u32 u4Tmp = 0;
printk("[CKGEN] IO AGENT TEST ------------------------------------------ \n");
IO_WRITE32(0x1000, 0x500, 0x55555555);
u4Tmp = IO_READ32(0x1000, 0x500);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x1500\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1500. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x0, 0x18, 0x55555555);
u4Tmp = IO_READ32(0x0, 0x18);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x18\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x18. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x0, 0x0408, 0x55555555);
u4Tmp = IO_READ32(0x0, 0x408);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x408\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x408. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x0, 0x0608, 0x55555555);
u4Tmp = IO_READ32(0x0, 0x608);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x608\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x608. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x0, 0x0a10, 0x55555555);
u4Tmp = IO_READ32(0x0, 0xa10);
if (u4Tmp == 0x00055555)
{
printk("[CKGEN] TEST PASS at 0xa10\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0xa10. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0x200, 0xaaaaffff);
u4Tmp = IO_READ32(0x1000, 0x200);
if (u4Tmp == 0xaaaaffff)
{
printk("[CKGEN] TEST PASS at 0x1200\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1200. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0x608, 0x05550555);
u4Tmp = IO_READ32(0x1000, 0x608);
if (u4Tmp == 0x05550555)
{
printk("[CKGEN] TEST PASS at 0x1608\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1608. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0x708, 0x55555555);
u4Tmp = IO_READ32(0x1000, 0x708);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x1708\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1708. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0xd00, 0x55555555);
u4Tmp = IO_READ32(0x1000, 0xd00);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x1d00\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1d00. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0xd00, 0xaaaaaaaa);
u4Tmp = IO_READ32(0x1000, 0xd00);
if (u4Tmp == 0xaaaaaaaa)
{
printk("[CKGEN] TEST PASS at 0x1d00\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1d00. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
printk("[CKGEN] IO AGENT TEST FINISH ------------------------------------------ \n");
return 0;
}
