static void gemini_unmask_irq(struct irq_data *d) { unsigned int mask; mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); mask |= (1 << d->irq); __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); }
static void gemini_mask_irq(unsigned int irq) { unsigned int mask; mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); mask &= ~(1 << irq); __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); }
void __init gemini_init_irq(void) { unsigned int i, mode = 0, level = 0; /* * Disable the idle handler by default since it is buggy * For more info see arch/arm/mach-gemini/idle.c */ disable_hlt(); request_resource(&iomem_resource, &irq_resource); for (i = 0; i < NR_IRQS; i++) { irq_set_chip(i, &gemini_irq_chip); if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { irq_set_handler(i, handle_edge_irq); mode |= 1 << i; level |= 1 << i; } else { irq_set_handler(i, handle_level_irq); } set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } /* Disable all interrupts */ __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); /* Set interrupt mode */ __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); }
void __init gemini_init_irq(void) { unsigned int i, mode = 0, level = 0; /* */ disable_hlt(); request_resource(&iomem_resource, &irq_resource); for (i = 0; i < NR_IRQS; i++) { irq_set_chip(i, &gemini_irq_chip); if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { irq_set_handler(i, handle_edge_irq); mode |= 1 << i; level |= 1 << i; } else { irq_set_handler(i, handle_level_irq); } set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } /* */ __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); /* */ __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); }
/** * write_i2c() - Write data to I2C client. * @dev: private data of I2C Driver * * This function writes data to I2C client */ static int write_i2c(struct nmk_i2c_dev *dev) { u32 status = 0; u32 mcr; u32 irq_mask = 0; int timeout; mcr = load_i2c_mcr_reg(dev); writel(mcr, dev->virtbase + I2C_MCR); /* load the current CR value */ writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, dev->virtbase + I2C_CR); /* enable the controller */ i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE); init_completion(&dev->xfer_complete); /* enable interrupts by settings the masks */ irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR); /* * check if we want to transfer a single or multiple bytes, if so * set the MTDWS bit (Master Transaction Done Without Stop) * to start repeated start operation */ if (dev->stop) irq_mask |= I2C_IT_MTD; else irq_mask |= I2C_IT_MTDWS; irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, dev->virtbase + I2C_IMSCR); timeout = wait_for_completion_interruptible_timeout( &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS)); if (timeout < 0) { dev_err(&dev->pdev->dev, "wait_for_completion_interruptible_timeout" "returned %d waiting for event\n", timeout); status = timeout; } if (timeout == 0) { /* controler has timedout, re-init the h/w */ dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n"); (void) init_hw(dev); status = -ETIMEDOUT; } return status; }
void disable_irq(int irq) { unsigned short pic; if(irq<8) pic=PIC1_MASK; else pic=PIC2_MASK; unsigned char mask = inportb(pic) | (IRQ_MASK(irq)); outportb(pic,mask); }
/** * read_i2c() - Read from I2C client device * @dev: private data of I2C Driver * * This function reads from i2c client device when controller is in * master mode. There is a completion timeout. If there is no transfer * before timeout error is returned. */ static int read_i2c(struct nmk_i2c_dev *dev) { u32 status = 0; u32 mcr; u32 irq_mask = 0; int timeout; mcr = load_i2c_mcr_reg(dev); writel(mcr, dev->virtbase + I2C_MCR); /* load the current CR value */ writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR, dev->virtbase + I2C_CR); /* enable the controller */ i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE); init_completion(&dev->xfer_complete); /* enable interrupts by setting the mask */ irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | I2C_IT_MAL | I2C_IT_BERR); if (dev->stop) irq_mask |= I2C_IT_MTD; else irq_mask |= I2C_IT_MTDWS; irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask, dev->virtbase + I2C_IMSCR); timeout = wait_for_completion_interruptible_timeout( &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS)); if (timeout < 0) { dev_err(&dev->pdev->dev, "wait_for_completion_interruptible_timeout" "returned %d waiting for event\n", timeout); status = timeout; } if (timeout == 0) { /* controler has timedout, re-init the h/w */ dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n"); (void) init_hw(dev); status = -ETIMEDOUT; } return status; }
static void i8259_init(struct atpic *pic, int slave) { int imr_addr; /* Reset the PIC and program with next four bytes. */ spinlock_enter(); #ifdef DEV_MCA /* MCA uses level triggered interrupts. */ if (MCA_system) outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4 | ICW1_LTIM); else #endif outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4); imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET; /* Start vector. */ outb(imr_addr, pic->at_intbase); /* * Setup slave links. For the master pic, indicate what line * the slave is configured on. For the slave indicate * which line on the master we are connected to. */ if (slave) outb(imr_addr, ICU_SLAVEID); else outb(imr_addr, IRQ_MASK(ICU_SLAVEID)); /* Set mode. */ if (slave) outb(imr_addr, SLAVE_MODE); else outb(imr_addr, MASTER_MODE); /* Set interrupt enable mask. */ outb(imr_addr, *pic->at_imen); /* Reset is finished, default to IRR on read. */ outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR); #ifndef PC98 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */ if (!slave) outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1); #endif spinlock_exit(); }
void pic_irq_ack(unsigned int irq) { u32 mask = IRQ_MASK(irq); debug("ack: %d\n", irq); out_be32((u32 *) IAR, mask); }
void pic_irq_disable(unsigned int irq) { u32 mask = IRQ_MASK(irq); debug("disable: %d\n", irq); out_be32((u32 *) CIE, mask); }
/** * clear_all_interrupts() - Clear all interrupts of I2C Controller * @dev: private data of I2C Driver */ static void clear_all_interrupts(struct nmk_i2c_dev *dev) { u32 mask; mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); writel(mask, dev->virtbase + I2C_ICR); }
/** * disable_all_interrupts() - Disable all interrupts of this I2c Bus * @dev: private data of I2C Driver */ static void disable_all_interrupts(struct nmk_i2c_dev *dev) { u32 mask = IRQ_MASK(0); writel(mask, dev->virtbase + I2C_IMSCR); }