void ir_reg_irda_fir_set_tx(TYPE_IR_SEND_KIND a_kind)
{
IR_WRITE_CR15(IR_CR15_OPT_IO_A_CNN_ENA);
IR_WRITE_CR0(IR_CR0_SEND_CNT_SEL);
IR_WRITE_CR1(IR_CR1_DEFSET);
IR_WRITE_CR2(IR_CR2_RX_OVERRUN_ERR_MSK |
IR_CR2_RX_FLM_ERR_MSK |
IR_CR2_RX_END_MSK |
IR_CR2_TIMER_INTRPT_MSK |
IR_CR2_RX_START_MSK);
IR_WRITE_CR10(IR_CR10_FIR_TX_MODE);
if (a_kind == IR_SEND_CONTINUE) {
IR_WRITE_CR11(IR_CR11_SEND_CONTINUE);
IR_WRITE_CR36(IR_CR36_FIR_INT_MODE);
} else {
IR_WRITE_CR11(IR_CR_CLEAR);
IR_WRITE_CR36(IR_CR_CLEAR);
}
IR_WRITE_CR26(IR_CR26_FIFO_RESET);
IR_WRITE_CR27(IR_CR27_FIFO_4M_TX_MODE);
}
void ir_reg_irda_sir_set_tx(TYPE_IR_SEND_KIND a_kind)
{
IR_WRITE_CR15(IR_CR15_OPT_IO_A_CNN_ENA);
IR_WRITE_CR0(IR_CR0_SEND_CNT_SEL);
IR_WRITE_CR20(IR_CR20_RX_CRC_ERR_MSK |
IR_CR20_RX_OVERRUN_ERR_MSK |
IR_CR20_RX_STOP_ERR_MSK |
IR_CR20_RX_PRTY_ERR_MSK |
IR_CR20_RX_END_MSK |
IR_CR20_TX_BUF_SP_ENA_MSK |
IR_CR20_TX_BUF_SP_MSK);
IR_WRITE_CR10(IR_CR10_SIR_TX_MODE);
IR_WRITE_CR36( IR_CR36_TX_END_TIMING2 );
if (a_kind == IR_SEND_CONTINUE) {
IR_WRITE_CR11(IR_CR11_SEND_CONTINUE);
} else {
IR_WRITE_CR11(IR_CR_CLEAR);
}
IR_WRITE_CR26(IR_CR26_FIFO_RESET);
IR_WRITE_CR27(IR_CR27_FIFO_TX_MODE);
}
void ir_reg_CR36_write(uint16 cr36_write_val)
{
IR_WRITE_CR36(cr36_write_val);
udelay(IR_CR36_DELAY);
}
