/*---------------------------------------------------------------------------* * ISACSX interrupt service routine *---------------------------------------------------------------------------*/ void isic_isacsx_irq(struct isic_softc *sc, int ista) { register u_char c = 0; register u_char istad = 0; NDBGL1(L1_F_MSG, "%s: ista = 0x%02x", device_xname(&sc->sc_dev), ista); /* was it an HDLC interrupt ? */ if (ista & ISACSX_ISTA_ICD) { istad = ISAC_READ(I_ISTAD); NDBGL1(L1_F_MSG, "%s: istad = 0x%02x", device_xname(&sc->sc_dev), istad); if(istad & (ISACSX_ISTAD_RFO|ISACSX_ISTAD_XMR|ISACSX_ISTAD_XDU)) { /* not really EXIR, but very similar */ c |= isic_isacsx_exir_hdlr(sc, istad); } } if(istad & ISACSX_ISTAD_RME) /* receive message end */ { register int rest; u_char rsta; /* get rx status register */ rsta = ISAC_READ(I_RSTAD); /* Check for Frame and CRC valid */ if((rsta & ISACSX_RSTAD_MASK) != (ISACSX_RSTAD_VFR|ISACSX_RSTAD_CRC)) { int error = 0; if(!(rsta & ISACSX_RSTAD_VFR)) /* VFR error */ { error++; NDBGL1(L1_I_ERR, "%s: Frame not valid error", device_xname(&sc->sc_dev)); } if(!(rsta & ISACSX_RSTAD_CRC)) /* CRC error */ { error++; NDBGL1(L1_I_ERR, "%s: CRC error", device_xname(&sc->sc_dev)); } if(rsta & ISACSX_RSTAD_RDO) /* ReceiveDataOverflow */ { error++; NDBGL1(L1_I_ERR, "%s: Data Overrun error", device_xname(&sc->sc_dev)); } if(rsta & ISACSX_RSTAD_RAB) /* ReceiveABorted */ { error++; NDBGL1(L1_I_ERR, "%s: Receive Aborted error", device_xname(&sc->sc_dev)); } if(error == 0) NDBGL1(L1_I_ERR, "%s: RME unknown error, RSTAD = 0x%02x!", device_xname(&sc->sc_dev), rsta); i4b_Dfreembuf(sc->sc_ibuf); c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES; sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; ISAC_WRITE(I_CMDRD, ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES); return; } rest = (ISAC_READ(I_RBCLD) & (ISACSX_FIFO_LEN-1)); if(rest == 0) rest = ISACSX_FIFO_LEN; if(sc->sc_ibuf == NULL) { if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL) sc->sc_ib = sc->sc_ibuf->m_data; else panic("isic_isacsx_irq: RME, i4b_Dgetmbuf returns NULL!\n"); sc->sc_ilen = 0; } if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest)) { ISAC_RDFIFO(sc->sc_ib, rest); /* the last byte contains status, strip it */ sc->sc_ilen += rest - 1; sc->sc_ibuf->m_pkthdr.len = sc->sc_ibuf->m_len = sc->sc_ilen; if(sc->sc_trace & TRACE_D_RX) { i4b_trace_hdr hdr; memset(&hdr, 0, sizeof hdr); hdr.type = TRC_CH_D; hdr.dir = FROM_NT; hdr.count = ++sc->sc_trace_dcount; isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data); } c |= ISACSX_CMDRD_RMC; if(sc->sc_intr_valid == ISIC_INTR_VALID && (((struct isdn_l3_driver*)sc->sc_l3token)->protocol != PROTOCOL_D64S)) { isdn_layer2_data_ind(&sc->sc_l2, sc->sc_l3token, sc->sc_ibuf); } else { i4b_Dfreembuf(sc->sc_ibuf); } } else { NDBGL1(L1_I_ERR, "RME, input buffer overflow!"); i4b_Dfreembuf(sc->sc_ibuf); c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES; } sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; } if(istad & ISACSX_ISTAD_RPF) /* receive fifo full */ { if(sc->sc_ibuf == NULL) { if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL) sc->sc_ib= sc->sc_ibuf->m_data; else panic("isic_isacsx_irq: RPF, i4b_Dgetmbuf returns NULL!\n"); sc->sc_ilen = 0; } if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISACSX_FIFO_LEN)) { ISAC_RDFIFO(sc->sc_ib, ISACSX_FIFO_LEN); sc->sc_ilen += ISACSX_FIFO_LEN; sc->sc_ib += ISACSX_FIFO_LEN; c |= ISACSX_CMDRD_RMC; } else { NDBGL1(L1_I_ERR, "RPF, input buffer overflow!"); i4b_Dfreembuf(sc->sc_ibuf); sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; c |= ISACSX_CMDRD_RMC|ISACSX_CMDRD_RRES; } } if(istad & ISACSX_ISTAD_XPR) /* transmit fifo empty (XPR bit set) */ { if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL)) { sc->sc_freeflag = sc->sc_freeflag2; sc->sc_obuf = sc->sc_obuf2; sc->sc_op = sc->sc_obuf->m_data; sc->sc_ol = sc->sc_obuf->m_len; sc->sc_obuf2 = NULL; #ifdef NOTDEF printf("ob2=%x, op=%x, ol=%d, f=%d #", sc->sc_obuf, sc->sc_op, sc->sc_ol, sc->sc_state); #endif } else { #ifdef NOTDEF printf("ob=%x, op=%x, ol=%d, f=%d #", sc->sc_obuf, sc->sc_op, sc->sc_ol, sc->sc_state); #endif } if(sc->sc_obuf) { ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISACSX_FIFO_LEN)); if(sc->sc_ol > ISACSX_FIFO_LEN) /* length > 32 ? */ { sc->sc_op += ISACSX_FIFO_LEN; /* bufferptr+32 */ sc->sc_ol -= ISACSX_FIFO_LEN; /* length - 32 */ c |= ISACSX_CMDRD_XTF; /* set XTF bit */ } else { if(sc->sc_freeflag) { i4b_Dfreembuf(sc->sc_obuf); sc->sc_freeflag = 0; } sc->sc_obuf = NULL; sc->sc_op = NULL; sc->sc_ol = 0; c |= ISACSX_CMDRD_XTF | ISACSX_CMDRD_XME; } } else { sc->sc_state &= ~ISAC_TX_ACTIVE; } } if(ista & ISACSX_ISTA_CIC) /* channel status change CISQ */ { register u_char ci; /* get command/indication rx register*/ ci = ISAC_READ(I_CIR0); /* C/I code change IRQ (flag already cleared by CIR0 read) */ if(ci & ISACSX_CIR0_CIC0) isic_isacsx_ind_hdlr(sc, (ci >> 4) & 0xf); } if(c) { ISAC_WRITE(I_CMDRD, c); } }
/*---------------------------------------------------------------------------* * * L2 -> L1: PH-DATA-REQUEST * ========================= * * parms: * unit physical interface unit number * m mbuf containing L2 frame to be sent out * freeflag MBUF_FREE: free mbuf here after having sent * it out * MBUF_DONTFREE: mbuf is freed by Layer 2 * returns: * ==0 fail, nothing sent out * !=0 ok, frame sent out * *---------------------------------------------------------------------------*/ int ifpi_ph_data_req(int unit, struct mbuf *m, int freeflag) { u_char cmd; struct l1_softc *sc = ifpi_scp[unit]; #ifdef NOTDEF NDBGL1(L1_PRIM, "PH-DATA-REQ, unit %d, freeflag=%d", unit, freeflag); #endif if(m == NULL) /* failsafe */ return (0); crit_enter(); if(sc->sc_I430state == ST_F3) /* layer 1 not running ? */ { NDBGL1(L1_I_ERR, "still in state F3!"); ifpi_ph_activate_req(unit); } if(sc->sc_state & ISAC_TX_ACTIVE) { if(sc->sc_obuf2 == NULL) { sc->sc_obuf2 = m; /* save mbuf ptr */ if(freeflag) sc->sc_freeflag2 = 1; /* IRQ must mfree */ else sc->sc_freeflag2 = 0; /* IRQ must not mfree */ NDBGL1(L1_I_MSG, "using 2nd ISAC TX buffer, state = %s", ifpi_printstate(sc)); if(sc->sc_trace & TRACE_D_TX) { i4b_trace_hdr_t hdr; hdr.unit = L0IFPIUNIT(unit); hdr.type = TRC_CH_D; hdr.dir = FROM_TE; hdr.count = ++sc->sc_trace_dcount; MICROTIME(hdr.time); i4b_l1_trace_ind(&hdr, m->m_len, m->m_data); } crit_exit(); return(1); } NDBGL1(L1_I_ERR, "No Space in TX FIFO, state = %s", ifpi_printstate(sc)); if(freeflag == MBUF_FREE) i4b_Dfreembuf(m); crit_exit(); return (0); } if(sc->sc_trace & TRACE_D_TX) { i4b_trace_hdr_t hdr; hdr.unit = L0IFPIUNIT(unit); hdr.type = TRC_CH_D; hdr.dir = FROM_TE; hdr.count = ++sc->sc_trace_dcount; MICROTIME(hdr.time); i4b_l1_trace_ind(&hdr, m->m_len, m->m_data); } sc->sc_state |= ISAC_TX_ACTIVE; /* set transmitter busy flag */ NDBGL1(L1_I_MSG, "ISAC_TX_ACTIVE set"); sc->sc_freeflag = 0; /* IRQ must NOT mfree */ ISAC_WRFIFO(m->m_data, min(m->m_len, ISAC_FIFO_LEN)); /* output to TX fifo */ if(m->m_len > ISAC_FIFO_LEN) /* message > 32 bytes ? */ { sc->sc_obuf = m; /* save mbuf ptr */ sc->sc_op = m->m_data + ISAC_FIFO_LEN; /* ptr for irq hdl */ sc->sc_ol = m->m_len - ISAC_FIFO_LEN; /* length for irq hdl */ if(freeflag) sc->sc_freeflag = 1; /* IRQ must mfree */ cmd = ISAC_CMDR_XTF; } else { sc->sc_obuf = NULL; sc->sc_op = NULL; sc->sc_ol = 0; if(freeflag) i4b_Dfreembuf(m); cmd = ISAC_CMDR_XTF | ISAC_CMDR_XME; } ISAC_WRITE(I_CMDR, cmd); ISACCMDRWRDELAY(); crit_exit(); return(1); }
/*---------------------------------------------------------------------------* * * L2 -> L1: PH-DATA-REQUEST * ========================= * * parms: * token softc of physical driver * m mbuf containing L2 frame to be sent out * freeflag MBUF_FREE: free mbuf here after having sent * it out * MBUF_DONTFREE: mbuf is freed by Layer 2 * returns: * ==0 fail, nothing sent out * !=0 ok, frame sent out * *---------------------------------------------------------------------------*/ static int isic_std_ph_data_req(isdn_layer1token token, struct mbuf *m, int freeflag) { struct isic_softc *sc = (struct isic_softc*)token; u_char cmd; int s; if (m == NULL) /* failsafe */ return (0); s = splnet(); if(sc->sc_I430state == ST_F3) /* layer 1 not running ? */ { NDBGL1(L1_I_ERR, "still in state F3!"); isic_std_ph_activate_req(token); } if(sc->sc_state & ISAC_TX_ACTIVE) { if(sc->sc_obuf2 == NULL) { sc->sc_obuf2 = m; /* save mbuf ptr */ if(freeflag) sc->sc_freeflag2 = 1; /* IRQ must mfree */ else sc->sc_freeflag2 = 0; /* IRQ must not mfree */ NDBGL1(L1_I_MSG, "using 2nd ISAC TX buffer, state = %s", isic_printstate(sc)); if(sc->sc_trace & TRACE_D_TX) { i4b_trace_hdr hdr; hdr.type = TRC_CH_D; hdr.dir = FROM_TE; hdr.count = ++sc->sc_trace_dcount; isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, m->m_len, m->m_data); } splx(s); return(1); } NDBGL1(L1_I_ERR, "No Space in TX FIFO, state = %s", isic_printstate(sc)); if(freeflag == MBUF_FREE) i4b_Dfreembuf(m); splx(s); return (0); } if(sc->sc_trace & TRACE_D_TX) { i4b_trace_hdr hdr; hdr.type = TRC_CH_D; hdr.dir = FROM_TE; hdr.count = ++sc->sc_trace_dcount; isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, m->m_len, m->m_data); } sc->sc_state |= ISAC_TX_ACTIVE; /* set transmitter busy flag */ NDBGL1(L1_I_MSG, "ISAC_TX_ACTIVE set"); sc->sc_freeflag = 0; /* IRQ must NOT mfree */ ISAC_WRFIFO(m->m_data, min(m->m_len, ISAC_FIFO_LEN)); /* output to TX fifo */ if(m->m_len > ISAC_FIFO_LEN) /* message > 32 bytes ? */ { sc->sc_obuf = m; /* save mbuf ptr */ sc->sc_op = m->m_data + ISAC_FIFO_LEN; /* ptr for irq hdl */ sc->sc_ol = m->m_len - ISAC_FIFO_LEN; /* length for irq hdl */ if(freeflag) sc->sc_freeflag = 1; /* IRQ must mfree */ cmd = ISAC_CMDR_XTF; } else { sc->sc_obuf = NULL; sc->sc_op = NULL; sc->sc_ol = 0; if(freeflag) i4b_Dfreembuf(m); cmd = ISAC_CMDR_XTF | ISAC_CMDR_XME; } ISAC_WRITE(I_CMDR, cmd); ISACCMDRWRDELAY(); splx(s); return(1); }
/*---------------------------------------------------------------------------* * ISAC interrupt service routine *---------------------------------------------------------------------------*/ void isic_isac_irq(struct isic_softc *sc, int ista) { register u_char c = 0; NDBGL1(L1_F_MSG, "%s: ista = 0x%02x", device_xname(&sc->sc_dev), ista); if(ista & ISAC_ISTA_EXI) /* extended interrupt */ { u_int8_t exirstat = ISAC_READ(I_EXIR); if (sc->sc_intr_valid == ISIC_INTR_VALID) c |= isic_isac_exir_hdlr(sc, exirstat); } if(ista & ISAC_ISTA_RME) /* receive message end */ { register int rest; u_char rsta; /* get rx status register */ rsta = ISAC_READ(I_RSTA); if((rsta & ISAC_RSTA_MASK) != 0x20) { int error = 0; if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */ { error++; NDBGL1(L1_I_ERR, "%s: CRC error", device_xname(&sc->sc_dev)); } if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */ { error++; NDBGL1(L1_I_ERR, "%s: Data Overrun error", device_xname(&sc->sc_dev)); } if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */ { error++; NDBGL1(L1_I_ERR, "%s: Receive Aborted error", device_xname(&sc->sc_dev)); } if(error == 0) { NDBGL1(L1_I_ERR, "%s: RME unknown error, RSTA = 0x%02x!", device_xname(&sc->sc_dev), rsta); } i4b_Dfreembuf(sc->sc_ibuf); c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES; sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES); ISACCMDRWRDELAY(); return; } rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1)); if(rest == 0) rest = ISAC_FIFO_LEN; if(sc->sc_ibuf == NULL) { if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL) sc->sc_ib = sc->sc_ibuf->m_data; else panic("isic_isac_irq: RME, i4b_Dgetmbuf returns NULL!"); sc->sc_ilen = 0; } if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest)) { ISAC_RDFIFO(sc->sc_ib, rest); sc->sc_ilen += rest; sc->sc_ibuf->m_pkthdr.len = sc->sc_ibuf->m_len = sc->sc_ilen; if(sc->sc_trace & TRACE_D_RX) { i4b_trace_hdr hdr; memset(&hdr, 0, sizeof hdr); hdr.type = TRC_CH_D; hdr.dir = FROM_NT; hdr.count = ++sc->sc_trace_dcount; isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data); } c |= ISAC_CMDR_RMC; if(sc->sc_intr_valid == ISIC_INTR_VALID && (((struct isdn_l3_driver*)sc->sc_l3token)->protocol != PROTOCOL_D64S)) { isdn_layer2_data_ind(&sc->sc_l2, sc->sc_l3token, sc->sc_ibuf); } else { i4b_Dfreembuf(sc->sc_ibuf); } } else { NDBGL1(L1_I_ERR, "RME, input buffer overflow!"); i4b_Dfreembuf(sc->sc_ibuf); c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES; } sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; } if(ista & ISAC_ISTA_RPF) /* receive fifo full */ { if(sc->sc_ibuf == NULL) { if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL) sc->sc_ib= sc->sc_ibuf->m_data; else panic("isic_isac_irq: RPF, i4b_Dgetmbuf returns NULL!"); sc->sc_ilen = 0; } if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN)) { ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN); sc->sc_ilen += ISAC_FIFO_LEN; sc->sc_ib += ISAC_FIFO_LEN; c |= ISAC_CMDR_RMC; } else { NDBGL1(L1_I_ERR, "RPF, input buffer overflow!"); i4b_Dfreembuf(sc->sc_ibuf); sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES; } } if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */ { if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL)) { sc->sc_freeflag = sc->sc_freeflag2; sc->sc_obuf = sc->sc_obuf2; sc->sc_op = sc->sc_obuf->m_data; sc->sc_ol = sc->sc_obuf->m_len; sc->sc_obuf2 = NULL; #ifdef NOTDEF printf("ob2=%x, op=%x, ol=%d, f=%d #", sc->sc_obuf, sc->sc_op, sc->sc_ol, sc->sc_state); #endif } else { #ifdef NOTDEF printf("ob=%x, op=%x, ol=%d, f=%d #", sc->sc_obuf, sc->sc_op, sc->sc_ol, sc->sc_state); #endif } if(sc->sc_obuf) { ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN)); if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */ { sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */ sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */ c |= ISAC_CMDR_XTF; /* set XTF bit */ } else { if(sc->sc_freeflag) { i4b_Dfreembuf(sc->sc_obuf); sc->sc_freeflag = 0; } sc->sc_obuf = NULL; sc->sc_op = NULL; sc->sc_ol = 0; c |= ISAC_CMDR_XTF | ISAC_CMDR_XME; } } else { sc->sc_state &= ~ISAC_TX_ACTIVE; } } if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */ { register u_char ci; /* get command/indication rx register*/ ci = ISAC_READ(I_CIRR); /* if S/Q IRQ, read SQC reg to clr SQC IRQ */ if(ci & ISAC_CIRR_SQC) (void) ISAC_READ(I_SQRR); /* C/I code change IRQ (flag already cleared by CIRR read) */ if(ci & ISAC_CIRR_CIC0) isic_isac_ind_hdlr(sc, (ci >> 2) & 0xf); } if(c) { ISAC_WRITE(I_CMDR, c); ISACCMDRWRDELAY(); } }
/*---------------------------------------------------------------------------* * ISAC interrupt service routine *---------------------------------------------------------------------------*/ void ifpnp_isac_irq(struct l1_softc *sc, int ista) { u_char c = 0; NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista); if(ista & ISAC_ISTA_EXI) /* extended interrupt */ { c |= ifpnp_isac_exir_hdlr(sc, ISAC_READ(I_EXIR)); } if(ista & ISAC_ISTA_RME) /* receive message end */ { int rest; u_char rsta; /* get rx status register */ rsta = ISAC_READ(I_RSTA); if((rsta & ISAC_RSTA_MASK) != 0x20) { int error = 0; if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */ { error++; NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit); } if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */ { error++; NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit); } if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */ { error++; NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit); } if(error == 0) NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTA = 0x%02x!", sc->sc_unit, rsta); i4b_Dfreembuf(sc->sc_ibuf); c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES; sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES); ISACCMDRWRDELAY(); return; } rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1)); if(rest == 0) rest = ISAC_FIFO_LEN; if(sc->sc_ibuf == NULL) { if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL) sc->sc_ib = sc->sc_ibuf->m_data; else panic("ifpnp_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n"); sc->sc_ilen = 0; } if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest)) { ISAC_RDFIFO(sc->sc_ib, rest); sc->sc_ilen += rest; sc->sc_ibuf->m_pkthdr.len = sc->sc_ibuf->m_len = sc->sc_ilen; if(sc->sc_trace & TRACE_D_RX) { i4b_trace_hdr_t hdr; hdr.unit = L0IFPNPUNIT(sc->sc_unit); hdr.type = TRC_CH_D; hdr.dir = FROM_NT; hdr.count = ++sc->sc_trace_dcount; MICROTIME(hdr.time); i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data); } c |= ISAC_CMDR_RMC; if(sc->sc_enabled && (ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S)) { i4b_l1_ph_data_ind(L0IFPNPUNIT(sc->sc_unit), sc->sc_ibuf); } else { i4b_Dfreembuf(sc->sc_ibuf); } } else { NDBGL1(L1_I_ERR, "RME, input buffer overflow!"); i4b_Dfreembuf(sc->sc_ibuf); c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES; } sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; } if(ista & ISAC_ISTA_RPF) /* receive fifo full */ { if(sc->sc_ibuf == NULL) { if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL) sc->sc_ib= sc->sc_ibuf->m_data; else panic("ifpnp_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n"); sc->sc_ilen = 0; } if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN)) { ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN); sc->sc_ilen += ISAC_FIFO_LEN; sc->sc_ib += ISAC_FIFO_LEN; c |= ISAC_CMDR_RMC; } else { NDBGL1(L1_I_ERR, "RPF, input buffer overflow!"); i4b_Dfreembuf(sc->sc_ibuf); sc->sc_ibuf = NULL; sc->sc_ib = NULL; sc->sc_ilen = 0; c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES; } } if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */ { if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL)) { sc->sc_freeflag = sc->sc_freeflag2; sc->sc_obuf = sc->sc_obuf2; sc->sc_op = sc->sc_obuf->m_data; sc->sc_ol = sc->sc_obuf->m_len; sc->sc_obuf2 = NULL; #ifdef NOTDEF kprintf("ob2=%x, op=%x, ol=%d, f=%d #", sc->sc_obuf, sc->sc_op, sc->sc_ol, sc->sc_state); #endif } else { #ifdef NOTDEF kprintf("ob=%x, op=%x, ol=%d, f=%d #", sc->sc_obuf, sc->sc_op, sc->sc_ol, sc->sc_state); #endif } if(sc->sc_obuf) { ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN)); if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */ { sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */ sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */ c |= ISAC_CMDR_XTF; /* set XTF bit */ } else { if(sc->sc_freeflag) { i4b_Dfreembuf(sc->sc_obuf); sc->sc_freeflag = 0; } sc->sc_obuf = NULL; sc->sc_op = NULL; sc->sc_ol = 0; c |= ISAC_CMDR_XTF | ISAC_CMDR_XME; } } else { sc->sc_state &= ~ISAC_TX_ACTIVE; } } if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */ { u_char ci; /* get command/indication rx register*/ ci = ISAC_READ(I_CIRR); /* if S/Q IRQ, read SQC reg to clr SQC IRQ */ if(ci & ISAC_CIRR_SQC) ISAC_READ(I_SQRR); /* C/I code change IRQ (flag already cleared by CIRR read) */ if(ci & ISAC_CIRR_CIC0) ifpnp_isac_ind_hdlr(sc, (ci >> 2) & 0xf); }