/**
* @brief Checks whether the specified DMAy Streamx interrupt has occurred or not.
* @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
* to 7 to select the DMA Stream.
* @param DMA_IT: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TCIFx: Streamx transfer complete interrupt
* @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt
* @arg DMA_IT_TEIFx: Streamx transfer error interrupt
* @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
* @arg DMA_IT_FEIFx: Streamx FIFO error interrupt
* Where x can be 0 to 7 to select the DMA Stream.
* @retval The new state of DMA_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
{
ITStatus bitstatus = RESET;
DMA_TypeDef* DMAy;
uint32_t tmpreg = 0, enablestatus = 0;
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
assert_param(IS_DMA_GET_IT(DMA_IT));
/* Determine the DMA to which belongs the stream */
if (DMAy_Streamx < DMA2_Stream0)
{
/* DMAy_Streamx belongs to DMA1 */
DMAy = DMA1;
}
else
{
/* DMAy_Streamx belongs to DMA2 */
DMAy = DMA2;
}
/* Check if the interrupt enable bit is in the CR or FCR register */
if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
{
/* Get the interrupt enable position mask in CR register */
tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);
/* Check the enable bit in CR register */
enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
}
/**
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
* @param DMA_IT: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
* @retval The new state of DMA_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMA_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMA_IT));
/* Calculate the used DMA */
if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR ;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR ;
}
/* Check the status of the specified DMA interrupt */
if ((tmpreg & DMA_IT) != (uint32_t)RESET)
{
/* DMA_IT is set */
bitstatus = SET;
}
else
{
/* DMA_IT is reset */
bitstatus = RESET;
}
/* Return the DMA_IT status */
return bitstatus;
}
/**
* @簡述 檢查指定的 DMA y 通道 x 中斷發生與否.
* @參數 DMA_IT: 指定的 DMA 中斷源.
* 這個參數可以是下面的值之一:
* DMA1_IT_GL1: DMA1 通道1 全局中斷.
* DMA1_IT_TC1: DMA1 通道1 傳輸完成中斷.
* DMA1_IT_HT1: DMA1 通道1 半傳輸中斷.
* DMA1_IT_TE1: DMA1 通道1 傳輸錯誤中斷.
* DMA1_IT_GL2: DMA1 通道2 全局中斷.
* DMA1_IT_TC2: DMA1 通道2 傳輸完成中斷.
* DMA1_IT_HT2: DMA1 通道2 半傳輸中斷.
* DMA1_IT_TE2: DMA1 通道2 傳輸錯誤中斷.
* DMA1_IT_GL3: DMA1 通道3 全局中斷.
* DMA1_IT_TC3: DMA1 通道3 傳輸完成中斷.
* DMA1_IT_HT3: DMA1 通道3 半傳輸中斷.
* DMA1_IT_TE3: DMA1 通道3 傳輸錯誤中斷.
* DMA1_IT_GL4: DMA1 通道4 全局中斷.
* DMA1_IT_TC4: DMA1 通道4 傳輸完成中斷.
* DMA1_IT_HT4: DMA1 通道4 半傳輸中斷.
* DMA1_IT_TE4: DMA1 通道4 傳輸錯誤中斷.
* DMA1_IT_GL5: DMA1 通道5 全局中斷.
* DMA1_IT_TC5: DMA1 通道5 傳輸完成中斷.
* DMA1_IT_HT5: DMA1 通道5 半傳輸中斷.
* DMA1_IT_TE5: DMA1 通道5 傳輸錯誤中斷.
* DMA1_IT_GL6: DMA1 通道6 全局中斷.
* DMA1_IT_TC6: DMA1 通道6 傳輸完成中斷.
* DMA1_IT_HT6: DMA1 通道6 半傳輸中斷.
* DMA1_IT_TE6: DMA1 通道6 傳輸錯誤中斷.
* DMA1_IT_GL7: DMA1 通道7 全局中斷.
* DMA1_IT_TC7: DMA1 通道7 傳輸完成中斷.
* DMA1_IT_HT7: DMA1 通道7 半傳輸中斷.
* DMA1_IT_TE7: DMA1 通道7 傳輸錯誤中斷.
* DMA2_IT_GL1: DMA2 通道1 全局中斷.
* DMA2_IT_TC1: DMA2 通道1 傳輸完成中斷.
* DMA2_IT_HT1: DMA2 通道1 半傳輸中斷.
* DMA2_IT_TE1: DMA2 通道1 傳輸錯誤中斷.
* DMA2_IT_GL2: DMA2 通道2 全局中斷.
* DMA2_IT_TC2: DMA2 通道2 傳輸完成中斷.
* DMA2_IT_HT2: DMA2 通道2 半傳輸中斷.
* DMA2_IT_TE2: DMA2 通道2 傳輸錯誤中斷.
* DMA2_IT_GL3: DMA2 通道3 全局中斷.
* DMA2_IT_TC3: DMA2 通道3 傳輸完成中斷.
* DMA2_IT_HT3: DMA2 通道3 半傳輸中斷.
* DMA2_IT_TE3: DMA2 通道3 傳輸錯誤中斷.
* DMA2_IT_GL4: DMA2 通道4 全局中斷.
* DMA2_IT_TC4: DMA2 通道4 傳輸完成中斷.
* DMA2_IT_HT4: DMA2 通道4 半傳輸中斷.
* DMA2_IT_TE4: DMA2 通道4 傳輸錯誤中斷.
* DMA2_IT_GL5: DMA2 通道5 全局中斷.
* DMA2_IT_TC5: DMA2 通道5 傳輸完成中斷.
* DMA2_IT_HT5: DMA2 通道5 半傳輸中斷.
* DMA2_IT_TE5: DMA2 通道5 傳輸錯誤中斷.
* @返回 DMA_IT 的新狀態 (SET 或 RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMA_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* 檢查參數 */
assert_param(IS_DMA_GET_IT(DMA_IT));
/* 計算使用的 DMA */
if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* 得到 DMA2 ISR 寄存器的值 */
tmpreg = DMA2->ISR ;
}
else
{
/* 得到 DMA1 ISR 寄存器的值 */
tmpreg = DMA1->ISR ;
}
/* 檢查指定的 DMA 中斷 */
if ((tmpreg & DMA_IT) != (uint32_t)RESET)
{
/* 設置 DMA_IT */
bitstatus = SET;
}
else
{
/* 復位 DMA_IT */
bitstatus = RESET;
}
/* 返回 DMA_IT 狀態 */
return bitstatus;
}
/**
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
* @param DMA_IT: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
*
* @note
* The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
* interrupts relative to the same channel is set (Transfer Complete,
* Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
* DMAy_IT_HTx or DMAy_IT_TEx).
*
* @retval The new state of DMA_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMA_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMA_IT));
/* Check the status of the specified DMA interrupt */
if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET) {
/* DMA_IT is set */
bitstatus = SET;
} else {
/* DMA_IT is reset */
bitstatus = RESET;
}
/* Return the DMA_IT status */
return bitstatus;
}
