static int s5p_mfc_wait_wakeup(struct s5p_mfc_dev *dev) { int ret; /* Send MFC wakeup command */ ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev); if (ret) { mfc_err("Failed to send command to MFC - timeout\n"); return ret; } /* Release reset signal to the RISC */ if (IS_MFCV6_PLUS(dev)) { dev->risc_on = 1; mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6); } else { mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET); } if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) { mfc_err("Failed to wakeup MFC\n"); return -EIO; } return ret; }
/* Reset the device */ int s5p_mfc_reset(struct s5p_mfc_dev *dev) { unsigned int mc_status; unsigned long timeout; int i; mfc_debug_enter(); if (IS_MFCV6_PLUS(dev)) { /* Zero Initialization of MFC registers */ mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6); mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6); mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6); for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++) mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4)); /* check bus reset control before reset */ if (dev->risc_on) if (s5p_mfc_bus_reset(dev)) return -EIO; /* Reset * set RISC_ON to 0 during power_on & wake_up. * V6 needs RISC_ON set to 0 during reset also. */ if ((!dev->risc_on) || (!IS_MFCV7_PLUS(dev))) mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6); mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6); mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6); } else { /* Stop procedure */ /* reset RISC */ mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET); /* All reset except for MC */ mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET); mdelay(10); timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT); /* Check MC status */ do { if (time_after(jiffies, timeout)) { mfc_err("Timeout while resetting MFC\n"); return -EIO; } mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS); } while (mc_status & 0x3); mfc_write(dev, 0x0, S5P_FIMV_SW_RESET); mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET); } mfc_debug_leave(); return 0; }
void s5p_mfc_init_hw_ops(struct s5p_mfc_dev *dev) { if (IS_MFCV6_PLUS(dev)) { s5p_mfc_ops = s5p_mfc_init_hw_ops_v6(); dev->warn_start = S5P_FIMV_ERR_WARNINGS_START_V6; } else { s5p_mfc_ops = s5p_mfc_init_hw_ops_v5(); dev->warn_start = S5P_FIMV_ERR_WARNINGS_START; } dev->mfc_ops = s5p_mfc_ops; }
/* Reset the device */ int s5p_mfc_reset(struct s5p_mfc_dev *dev) { unsigned int mc_status; unsigned long timeout; int i; mfc_debug_enter(); if (IS_MFCV6_PLUS(dev)) { /* Reset IP */ /* except RISC, reset */ mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET_V6); /* reset release */ mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET_V6); /* Zero Initialization of MFC registers */ mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6); mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6); mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6); for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++) mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4)); /* Reset */ mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6); mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6); mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6); } else { /* Stop procedure */ /* reset RISC */ mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET); /* All reset except for MC */ mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET); mdelay(10); timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT); /* Check MC status */ do { if (time_after(jiffies, timeout)) { mfc_err("Timeout while resetting MFC\n"); return -EIO; } mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS); } while (mc_status & 0x3); mfc_write(dev, 0x0, S5P_FIMV_SW_RESET); mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET); } mfc_debug_leave(); return 0; }
static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev) { if (IS_MFCV6_PLUS(dev)) { /* Zero initialization should be done before RESET. * Nothing to do here. */ } else { mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID); mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID); mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD); } }
static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev) { if (IS_MFCV6_PLUS(dev)) { mfc_write(dev, dev->bank1, S5P_FIMV_RISC_BASE_ADDRESS_V6); mfc_debug(2, "Base Address : %pad\n", &dev->bank1); } else { mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A); mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B); mfc_debug(2, "Bank1: %pad, Bank2: %pad\n", &dev->bank1, &dev->bank2); } }
int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) { int ret; mfc_debug_enter(); /* 0. MFC reset */ mfc_debug(2, "MFC reset..\n"); s5p_mfc_clock_on(); ret = s5p_mfc_reset(dev); if (ret) { mfc_err("Failed to reset MFC - timeout\n"); return ret; } mfc_debug(2, "Done MFC reset..\n"); /* 1. Set DRAM base Addr */ s5p_mfc_init_memctrl(dev); /* 2. Initialize registers of channel I/F */ s5p_mfc_clear_cmds(dev); s5p_mfc_clean_dev_int_flags(dev); /* 3. Initialize firmware */ ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev); if (ret) { mfc_err("Failed to send command to MFC - timeout\n"); return ret; } /* 4. Release reset signal to the RISC */ if (IS_MFCV6_PLUS(dev)) mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6); else mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET); mfc_debug(2, "Ok, now will write a command to wakeup the system\n"); if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) { mfc_err("Failed to load firmware\n"); return -EIO; } s5p_mfc_clock_off(); dev->int_cond = 0; if (dev->int_err != 0 || dev->int_type != S5P_MFC_R2H_CMD_WAKEUP_RET) { /* Failure. */ mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err, dev->int_type); return -EIO; } mfc_debug_leave(); return 0; }
void s5p_mfc_init_regs(struct s5p_mfc_dev *dev) { if (IS_MFCV6_PLUS(dev)) dev->mfc_regs = s5p_mfc_init_regs_v6_plus(dev); }
/* Initialize hardware */ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) { unsigned int ver; int ret; mfc_debug_enter(); if (!dev->fw_virt_addr) { mfc_err("Firmware memory is not allocated.\n"); return -EINVAL; } /* 0. MFC reset */ mfc_debug(2, "MFC reset..\n"); s5p_mfc_clock_on(); ret = s5p_mfc_reset(dev); if (ret) { mfc_err("Failed to reset MFC - timeout\n"); return ret; } mfc_debug(2, "Done MFC reset..\n"); /* 1. Set DRAM base Addr */ s5p_mfc_init_memctrl(dev); /* 2. Initialize registers of channel I/F */ s5p_mfc_clear_cmds(dev); /* 3. Release reset signal to the RISC */ s5p_mfc_clean_dev_int_flags(dev); if (IS_MFCV6_PLUS(dev)) mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6); else mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET); mfc_debug(2, "Will now wait for completion of firmware transfer\n"); if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) { mfc_err("Failed to load firmware\n"); s5p_mfc_reset(dev); s5p_mfc_clock_off(); return -EIO; } s5p_mfc_clean_dev_int_flags(dev); /* 4. Initialize firmware */ ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev); if (ret) { mfc_err("Failed to send command to MFC - timeout\n"); s5p_mfc_reset(dev); s5p_mfc_clock_off(); return ret; } mfc_debug(2, "Ok, now will wait for completion of hardware init\n"); if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) { mfc_err("Failed to init hardware\n"); s5p_mfc_reset(dev); s5p_mfc_clock_off(); return -EIO; } dev->int_cond = 0; if (dev->int_err != 0 || dev->int_type != S5P_MFC_R2H_CMD_SYS_INIT_RET) { /* Failure. */ mfc_err("Failed to init firmware - error: %d int: %d\n", dev->int_err, dev->int_type); s5p_mfc_reset(dev); s5p_mfc_clock_off(); return -EIO; } if (IS_MFCV6_PLUS(dev)) ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6); else ver = mfc_read(dev, S5P_FIMV_FW_VERSION); mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n", (ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF); s5p_mfc_clock_off(); mfc_debug_leave(); return 0; }