/**
Dump the resourc map of the bridge device.
@param[in] BridgeResource Resource descriptor of the bridge device.
**/
VOID
DumpBridgeResource (
IN PCI_RESOURCE_NODE *BridgeResource
)
{
LIST_ENTRY *Link;
PCI_RESOURCE_NODE *Resource;
PCI_BAR *Bar;
if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {
DEBUG ((
EFI_D_INFO, "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",
mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],
BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,
BridgeResource->Length, BridgeResource->Alignment
));
for ( Link = BridgeResource->ChildList.ForwardLink
; Link != &BridgeResource->ChildList
; Link = Link->ForwardLink
) {
Resource = RESOURCE_NODE_FROM_LINK (Link);
if (Resource->ResourceUsage == PciResUsageTypical) {
Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;
DEBUG ((
EFI_D_INFO, " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s ",
Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,
IS_PCI_BRIDGE (&Resource->PciDev->Pci) ? L"PPB" :
IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :
L"PCI"
));
if ((!IS_PCI_BRIDGE (&Resource->PciDev->Pci) && !IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci)) ||
(IS_PCI_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < PPB_IO_RANGE)) ||
(IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < P2C_MEM_1))
) {
//
// The resource requirement comes from the device itself.
//
DEBUG ((
EFI_D_INFO, " [%02x|%02x|%02x:%02x]\n",
Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
Resource->PciDev->FunctionNumber, Bar[Resource->Bar].Offset
));
} else {
//
// The resource requirement comes from the subordinate devices.
//
DEBUG ((
EFI_D_INFO, " [%02x|%02x|%02x:**]\n",
Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
Resource->PciDev->FunctionNumber
));
}
} else {
DEBUG ((EFI_D_INFO, " Padding:Length = 0x%lx;\tAlignment = 0x%lx\n", Resource->Length, Resource->Alignment));
}
}
}
}
/**
Remove rejected pci device from specific root bridge
handle.
@param RootBridgeHandle Specific parent root bridge handle.
@param Bridge Bridge device instance.
**/
VOID
RemoveRejectedPciDevices (
IN EFI_HANDLE RootBridgeHandle,
IN PCI_IO_DEVICE *Bridge
)
{
PCI_IO_DEVICE *Temp;
LIST_ENTRY *CurrentLink;
LIST_ENTRY *LastLink;
if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
return;
}
CurrentLink = Bridge->ChildList.ForwardLink;
while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
if (IS_PCI_BRIDGE (&Temp->Pci)) {
//
// Remove rejected devices recusively
//
RemoveRejectedPciDevices (RootBridgeHandle, Temp);
} else {
//
// Skip rejection for all PPBs, while detect rejection for others
//
if (IsPciDeviceRejected (Temp)) {
//
// For P2C, remove all devices on it
//
if (!IsListEmpty (&Temp->ChildList)) {
RemoveAllPciDeviceOnBridge (RootBridgeHandle, Temp);
}
//
// Finally remove itself
//
LastLink = CurrentLink->BackLink;
RemoveEntryList (CurrentLink);
FreePciDevice (Temp);
CurrentLink = LastLink;
}
}
CurrentLink = CurrentLink->ForwardLink;
}
}
EFI_STATUS
GetOpRomInfo (
IN PCI_IO_DEVICE *PciIoDevice
)
/*++
Routine Description:
Arguments:
Returns:
--*/
{
UINT8 RomBarIndex;
UINT32 AllOnes;
UINT64 Address;
EFI_STATUS Status;
UINT8 Bus;
UINT8 Device;
UINT8 Function;
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
Bus = PciIoDevice->BusNumber;
Device = PciIoDevice->DeviceNumber;
Function = PciIoDevice->FunctionNumber;
PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
//
// offset is 0x30 if is not ppb
//
//
// 0x30
//
RomBarIndex = PCI_EXPANSION_ROM_BASE;
if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
//
// if is ppb
//
//
// 0x38
//
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
//
// the bit0 is 0 to prevent the enabling of the Rom address decoder
//
AllOnes = 0xfffffffe;
Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);
Status = PciRootBridgeIo->Pci.Write (
PciRootBridgeIo,
EfiPciWidthUint32,
Address,
1,
&AllOnes
);
if (EFI_ERROR (Status)) {
return Status;
}
//
// read back
//
Status = PciRootBridgeIo->Pci.Read (
PciRootBridgeIo,
EfiPciWidthUint32,
Address,
1,
&AllOnes
);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Bits [1, 10] are reserved
//
AllOnes &= 0xFFFFF800;
if ((AllOnes == 0) || (AllOnes == 0xFFFFF800)) {
return EFI_NOT_FOUND;
}
DEBUG ((EFI_D_ERROR, "PCIBUS: GetOpRomInfo: OPROM detected!\n"));
DEBUG ((EFI_D_ERROR, "PCIBUS: GetOpRomInfo: B-%x, D-%x, F-%x\n", (UINTN)Bus, (UINTN)Device, (UINTN)Function));
PciIoDevice->RomSize = (UINT64) ((~AllOnes) + 1);
return EFI_SUCCESS;
}
EFI_STATUS
LoadOpRomImage (
IN PCI_IO_DEVICE *PciDevice,
IN UINT64 ReservedMemoryBase
)
/*++
Routine Description:
Load option rom image for specified PCI device
Arguments:
Returns:
--*/
{
UINT8 RomBarIndex;
UINT8 Indicator;
UINT16 OffsetPcir;
UINT32 RomBarOffset;
UINT32 RomBar;
EFI_STATUS retStatus;
BOOLEAN FirstCheck;
UINT8 *Image;
PCI_EXPANSION_ROM_HEADER *RomHeader;
PCI_DATA_STRUCTURE *RomPcir;
UINT64 RomSize;
UINT64 RomImageSize;
UINT32 LegacyImageLength;
UINT8 *RomInMemory;
UINT8 CodeType;
RomSize = PciDevice->RomSize;
Indicator = 0;
RomImageSize = 0;
RomInMemory = NULL;
CodeType = 0xFF;
//
// Get the RomBarIndex
//
//
// 0x30
//
RomBarIndex = PCI_EXPANSION_ROM_BASE;
if (IS_PCI_BRIDGE (&(PciDevice->Pci))) {
//
// if is ppb
//
//
// 0x38
//
RomBarIndex = PCI_BRIDGE_ROMBAR;
}
//
// Allocate memory for Rom header and PCIR
//
RomHeader = AllocatePool (sizeof (PCI_EXPANSION_ROM_HEADER));
if (RomHeader == NULL) {
return EFI_OUT_OF_RESOURCES;
}
RomPcir = AllocatePool (sizeof (PCI_DATA_STRUCTURE));
if (RomPcir == NULL) {
gBS->FreePool (RomHeader);
return EFI_OUT_OF_RESOURCES;
}
RomBar = (UINT32)ReservedMemoryBase;
//
// Enable RomBar
//
RomDecode (PciDevice, RomBarIndex, RomBar, TRUE);
RomBarOffset = RomBar;
retStatus = EFI_NOT_FOUND;
FirstCheck = TRUE;
LegacyImageLength = 0;
do {
PciDevice->PciRootBridgeIo->Mem.Read (
PciDevice->PciRootBridgeIo,
EfiPciWidthUint8,
RomBarOffset,
sizeof (PCI_EXPANSION_ROM_HEADER),
(UINT8 *) RomHeader
);
if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
RomBarOffset = RomBarOffset + 512;
if (FirstCheck) {
break;
} else {
RomImageSize = RomImageSize + 512;
continue;
}
}
FirstCheck = FALSE;
OffsetPcir = RomHeader->PcirOffset;
//
// If the pointer to the PCI Data Structure is invalid, no further images can be located.
// The PCI Data Structure must be DWORD aligned.
//
if (OffsetPcir == 0 ||
(OffsetPcir & 3) != 0 ||
RomImageSize + OffsetPcir + sizeof (PCI_DATA_STRUCTURE) > RomSize) {
break;
}
PciDevice->PciRootBridgeIo->Mem.Read (
PciDevice->PciRootBridgeIo,
EfiPciWidthUint8,
RomBarOffset + OffsetPcir,
sizeof (PCI_DATA_STRUCTURE),
(UINT8 *) RomPcir
);
//
// If a valid signature is not present in the PCI Data Structure, no further images can be located.
//
if (RomPcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
break;
}
if (RomImageSize + RomPcir->ImageLength * 512 > RomSize) {
break;
}
if (RomPcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
LegacyImageLength = ((UINT32)((EFI_LEGACY_EXPANSION_ROM_HEADER *)RomHeader)->Size512) * 512;
}
Indicator = RomPcir->Indicator;
RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
} while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize));
//
// Some Legacy Cards do not report the correct ImageLength so used the maximum
// of the legacy length and the PCIR Image Length
//
if (CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
RomImageSize = MAX (RomImageSize, LegacyImageLength);
}
if (RomImageSize > 0) {
retStatus = EFI_SUCCESS;
Image = AllocatePool ((UINT32) RomImageSize);
if (Image == NULL) {
RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
gBS->FreePool (RomHeader);
gBS->FreePool (RomPcir);
return EFI_OUT_OF_RESOURCES;
}
//
// Copy Rom image into memory
//
PciDevice->PciRootBridgeIo->Mem.Read (
PciDevice->PciRootBridgeIo,
EfiPciWidthUint8,
RomBar,
(UINT32) RomImageSize,
Image
);
RomInMemory = Image;
}
RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
PciDevice->PciIo.RomSize = RomImageSize;
PciDevice->PciIo.RomImage = RomInMemory;
//
// Free allocated memory
//
gBS->FreePool (RomHeader);
gBS->FreePool (RomPcir);
return retStatus;
}
EFI_STATUS
DetermineDeviceAttribute (
IN PCI_IO_DEVICE *PciIoDevice
)
/*++
Routine Description:
Determine the related attributes of all devices under a Root Bridge
Arguments:
Returns:
None
--*/
{
UINT16 Command;
UINT16 BridgeControl;
Command = 0;
PciIoDevice->Supports |= EFI_PCI_DEVICE_ENABLE;
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
if (IS_PCI_VGA (&(PciIoDevice->Pci))){
//
// If the device is VGA, VGA related Attributes are supported
//
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO ;
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY ;
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_IO ;
}
if(IS_ISA_BRIDGE(&(PciIoDevice->Pci)) || IS_INTEL_ISA_BRIDGE(&(PciIoDevice->Pci))) {
//
// If the devie is a ISA Bridge, set the two attributes
//
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO;
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;
}
if (IS_PCI_GFX (&(PciIoDevice->Pci))) {
//
// If the device is GFX, then only set the EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
// attribute
//
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO ;
}
//
// If the device is IDE, IDE related attributes are supported
//
if (IS_PCI_IDE (&(PciIoDevice->Pci))) {
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO ;
PciIoDevice->Supports |= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO ;
}
PciReadCommandRegister(PciIoDevice, &Command);
if (Command & EFI_PCI_COMMAND_IO_SPACE) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_IO;
}
if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_MEMORY;
}
if (Command & EFI_PCI_COMMAND_BUS_MASTER) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER;
}
if (IS_PCI_BRIDGE (&(PciIoDevice->Pci)) ||
IS_CARDBUS_BRIDGE (&(PciIoDevice->Pci))){
//
// If it is a PPB, read the Bridge Control Register to determine
// the relevant attributes
//
BridgeControl = 0;
PciReadBridgeControlRegister(PciIoDevice, &BridgeControl);
//
// Determine whether the ISA bit is set
// If ISA Enable on Bridge is set, the PPB
// will block forwarding 0x100-0x3ff for each 1KB in the
// first 64KB I/O range.
//
if ((BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA) != 0) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;
}
//
// Determine whether the VGA bit is set
// If it is set, the bridge is set to decode VGA memory range
// and palette register range
//
if (IS_PCI_VGA (&(PciIoDevice->Pci)) &&BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_IO;
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY;
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
}
//
// if the palette snoop bit is set, then the brige is set to
// decode palette IO write
//
if (Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
}
}
return EFI_SUCCESS;
}
EFI_STATUS
PciSearchDevice (
IN PCI_IO_DEVICE *Bridge,
IN PCI_TYPE00 *Pci,
IN UINT8 Bus,
IN UINT8 Device,
IN UINT8 Func,
OUT PCI_IO_DEVICE **PciDevice
)
/*++
Routine Description:
Search required device.
Arguments:
Bridge - A pointer to the PCI_IO_DEVICE.
Pci - A pointer to the PCI_TYPE00.
Bus - Bus number.
Device - Device number.
Func - Function number.
PciDevice - The Required pci device.
Returns:
Status code.
--*/
{
PCI_IO_DEVICE *PciIoDevice;
PciIoDevice = NULL;
if (!IS_PCI_BRIDGE (Pci)) {
if (IS_CARDBUS_BRIDGE (Pci)) {
PciIoDevice = GatherP2CInfo (
Bridge->PciRootBridgeIo,
Pci,
Bus,
Device,
Func
);
if ((PciIoDevice != NULL) && (gFullEnumeration == TRUE)) {
InitializeP2C (PciIoDevice);
}
} else {
//
// Create private data for Pci Device
//
PciIoDevice = GatherDeviceInfo (
Bridge->PciRootBridgeIo,
Pci,
Bus,
Device,
Func
);
}
} else {
//
// Create private data for PPB
//
PciIoDevice = GatherPPBInfo (
Bridge->PciRootBridgeIo,
Pci,
Bus,
Device,
Func
);
//
// Special initialization for PPB including making the PPB quiet
//
if ((PciIoDevice != NULL) && (gFullEnumeration == TRUE)) {
InitializePPB (PciIoDevice);
}
}
if (!PciIoDevice) {
return EFI_OUT_OF_RESOURCES;
}
//
// Create a device path for this PCI device and store it into its private data
//
CreatePciDevicePath(
Bridge->DevicePath,
PciIoDevice
);
//
// Detect this function has option rom
//
if (gFullEnumeration) {
if (!IS_CARDBUS_BRIDGE (Pci)) {
GetOpRomInfo (PciIoDevice);
}
ResetPowerManagementFeature (PciIoDevice);
}
else {
PciRomGetRomResourceFromPciOptionRomTable (
&gPciBusDriverBinding,
PciIoDevice->PciRootBridgeIo,
PciIoDevice
);
}
//
// Insert it into a global tree for future reference
//
InsertPciDevice (Bridge, PciIoDevice);
//
// Determine PCI device attributes
//
DetermineDeviceAttribute (PciIoDevice);
if (PciDevice != NULL) {
*PciDevice = PciIoDevice;
}
return EFI_SUCCESS;
}
EFI_STATUS
PciPciDeviceInfoCollector (
IN PCI_IO_DEVICE *Bridge,
UINT8 StartBusNumber
)
/*++
Routine Description:
Arguments:
Returns:
None
--*/
{
EFI_STATUS Status;
PCI_TYPE00 Pci;
UINT8 Device;
UINT8 Func;
UINT8 SecBus;
PCI_IO_DEVICE *PciIoDevice;
EFI_PCI_IO_PROTOCOL *PciIo;
Status = EFI_SUCCESS;
SecBus = 0;
for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
//
// Check to see whether PCI device is present
//
Status = PciDevicePresent (
Bridge->PciRootBridgeIo,
&Pci,
(UINT8) StartBusNumber,
(UINT8) Device,
(UINT8) Func
);
if (!EFI_ERROR (Status)) {
//
// Collect all the information about the PCI device discovered
//
Status = PciSearchDevice (
Bridge,
&Pci,
(UINT8) StartBusNumber,
Device,
Func,
&PciIoDevice
);
//
// Recursively scan PCI busses on the other side of PCI-PCI bridges
//
//
if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
//
// If it is PPB, we need to get the secondary bus to continue the enumeration
//
PciIo = &(PciIoDevice->PciIo);
Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &SecBus);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Deep enumerate the next level bus
//
Status = PciPciDeviceInfoCollector (
PciIoDevice,
(UINT8) (SecBus)
);
}
if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
//
// Skip sub functions, this is not a multi function device
//
Func = PCI_MAX_FUNC;
}
}
}
}
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
InitializePcatPciRootBridge (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
/*++
Routine Description:
Initializes the PCI Root Bridge Controller
Arguments:
ImageHandle -
SystemTable -
Returns:
None
--*/
{
EFI_STATUS Status;
PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
UINTN PciSegmentIndex;
UINTN PciRootBridgeIndex;
UINTN PrimaryBusIndex;
UINTN NumberOfPciRootBridges;
UINTN NumberOfPciDevices;
UINTN Device;
UINTN Function;
UINT16 VendorId;
PCI_TYPE02 PciConfigurationHeader;
UINT64 Address;
UINT64 Value;
UINT64 Base;
UINT64 Limit;
//
// Initialize gCpuIo now since the chipset init code requires it.
//
Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)&gCpuIo);
ASSERT_EFI_ERROR (Status);
//
// Initialize variables required to search all PCI segments for PCI devices
//
PciSegmentIndex = 0;
PciRootBridgeIndex = 0;
NumberOfPciRootBridges = 0;
PrimaryBusIndex = 0;
while (PciSegmentIndex <= PCI_MAX_SEGMENT) {
PrivateData = NULL;
Status = gBS->AllocatePool(
EfiBootServicesData,
sizeof (PCAT_PCI_ROOT_BRIDGE_INSTANCE),
(VOID **)&PrivateData
);
if (EFI_ERROR (Status)) {
goto Done;
}
ZeroMem (PrivateData, sizeof (PCAT_PCI_ROOT_BRIDGE_INSTANCE));
//
// Initialize the signature of the private data structure
//
PrivateData->Signature = PCAT_PCI_ROOT_BRIDGE_SIGNATURE;
PrivateData->Handle = NULL;
PrivateData->DevicePath = NULL;
InitializeListHead (&PrivateData->MapInfo);
//
// Initialize the PCI root bridge number and the bus range for that root bridge
//
PrivateData->RootBridgeNumber = (UINT32)PciRootBridgeIndex;
PrivateData->PrimaryBus = (UINT32)PrimaryBusIndex;
PrivateData->SubordinateBus = (UINT32)PrimaryBusIndex;
PrivateData->IoBase = 0xffffffff;
PrivateData->MemBase = 0xffffffff;
PrivateData->Mem32Base = 0xffffffffffffffffULL;
PrivateData->Pmem32Base = 0xffffffffffffffffULL;
PrivateData->Mem64Base = 0xffffffffffffffffULL;
PrivateData->Pmem64Base = 0xffffffffffffffffULL;
//
// The default mechanism for performing PCI Configuration cycles is to
// use the I/O ports at 0xCF8 and 0xCFC. This is only used for IA-32.
// IPF uses SAL calls to perform PCI COnfiguration cycles
//
PrivateData->PciAddress = 0xCF8;
PrivateData->PciData = 0xCFC;
//
// Get the physical I/O base for performing PCI I/O cycles
// For IA-32, this is always 0, because IA-32 has IN and OUT instructions
// For IPF, a SAL call is made to retrieve the base address for PCI I/O cycles
//
Status = PcatRootBridgeIoGetIoPortMapping (
&PrivateData->PhysicalIoBase,
&PrivateData->PhysicalMemoryBase
);
if (EFI_ERROR (Status)) {
goto Done;
}
//
// Get PCI Express Base Address
//
PrivateData->PciExpressBaseAddress = GetPciExpressBaseAddressForRootBridge (PciSegmentIndex, PciRootBridgeIndex);
/* if (PrivateData->PciExpressBaseAddress != 0) {
DEBUG ((EFI_D_ERROR, "PCIE Base - 0x%lx\n", PrivateData->PciExpressBaseAddress));
}
*/
//
// Create a lock for performing PCI Configuration cycles
//
EfiInitializeLock (&PrivateData->PciLock, TPL_HIGH_LEVEL);
//
// Initialize the attributes for this PCI root bridge
//
PrivateData->Attributes = 0;
//
// Build the EFI Device Path Protocol instance for this PCI Root Bridge
//
Status = PcatRootBridgeDevicePathConstructor (&PrivateData->DevicePath, PciRootBridgeIndex, (BOOLEAN)((PrivateData->PciExpressBaseAddress != 0) ? TRUE : FALSE));
if (EFI_ERROR (Status)) {
goto Done;
}
//
// Build the PCI Root Bridge I/O Protocol instance for this PCI Root Bridge
//
Status = PcatRootBridgeIoConstructor (&PrivateData->Io, PciSegmentIndex);
if (EFI_ERROR (Status)) {
goto Done;
}
//
// Scan all the PCI devices on the primary bus of the PCI root bridge
//
for (Device = 0, NumberOfPciDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
//
// Compute the PCI configuration address of the PCI device to probe
//
Address = EFI_PCI_ADDRESS (PrimaryBusIndex, Device, Function, 0);
//
// Read the Vendor ID from the PCI Configuration Header
//
Status = PrivateData->Io.Pci.Read (
&PrivateData->Io,
EfiPciWidthUint16,
Address,
sizeof (VendorId) / sizeof (UINT16),
&VendorId
);
if ((EFI_ERROR (Status)) || ((VendorId == 0xffff) && (Function == 0))) {
//
// If the PCI Configuration Read fails, or a PCI device does not exist, then
// skip this entire PCI device
//
break;
}
if (VendorId == 0xffff) {
//
// If PCI function != 0, VendorId == 0xFFFF, we continue to search PCI function.
//
continue;
}
//
// Read the entire PCI Configuration Header
//
Status = PrivateData->Io.Pci.Read (
&PrivateData->Io,
EfiPciWidthUint16,
Address,
sizeof (PciConfigurationHeader) / sizeof (UINT16),
&PciConfigurationHeader
);
if (EFI_ERROR (Status)) {
//
// If the entire PCI Configuration Header can not be read, then skip this entire PCI device
//
break;
}
//
// Increment the number of PCI device found on the primary bus of the PCI root bridge
//
NumberOfPciDevices++;
//
// Look for devices with the VGA Palette Snoop enabled in the COMMAND register of the PCI Config Header
//
if (PciConfigurationHeader.Hdr.Command & 0x20) {
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
}
//
// If the device is a PCI-PCI Bridge, then look at the Subordinate Bus Number
//
if (IS_PCI_BRIDGE(&PciConfigurationHeader)) {
//
// Get the Bus range that the PPB is decoding
//
if (PciConfigurationHeader.Bridge.P2PBridge.SubordinateBus > PrivateData->SubordinateBus) {
//
// If the suborinate bus number of the PCI-PCI bridge is greater than the PCI root bridge's
// current subordinate bus number, then update the PCI root bridge's subordinate bus number
//
PrivateData->SubordinateBus = PciConfigurationHeader.Bridge.P2PBridge.SubordinateBus;
}
//
// Get the I/O range that the PPB is decoding
//
Value = PciConfigurationHeader.Bridge.P2PBridge.IoBase & 0x0f;
Base = ((UINT32)PciConfigurationHeader.Bridge.P2PBridge.IoBase & 0xf0) << 8;
Limit = (((UINT32)PciConfigurationHeader.Bridge.P2PBridge.IoLimit & 0xf0) << 8) | 0x0fff;
if (Value == 0x01) {
Base |= ((UINT32)PciConfigurationHeader.Bridge.P2PBridge.IoBaseUpper16 << 16);
Limit |= ((UINT32)PciConfigurationHeader.Bridge.P2PBridge.IoLimitUpper16 << 16);
}
if (Base < Limit) {
if (PrivateData->IoBase > Base) {
PrivateData->IoBase = Base;
}
if (PrivateData->IoLimit < Limit) {
PrivateData->IoLimit = Limit;
}
}
//
// Get the Memory range that the PPB is decoding
//
Base = ((UINT32)PciConfigurationHeader.Bridge.P2PBridge.MemoryBase & 0xfff0) << 16;
Limit = (((UINT32)PciConfigurationHeader.Bridge.P2PBridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
if (Base < Limit) {
if (PrivateData->MemBase > Base) {
PrivateData->MemBase = Base;
}
if (PrivateData->MemLimit < Limit) {
PrivateData->MemLimit = Limit;
}
if (PrivateData->Mem32Base > Base) {
PrivateData->Mem32Base = Base;
}
if (PrivateData->Mem32Limit < Limit) {
PrivateData->Mem32Limit = Limit;
}
}
//
// Get the Prefetchable Memory range that the PPB is decoding
//
Value = PciConfigurationHeader.Bridge.P2PBridge.PrefetchableMemoryBase & 0x0f;
Base = ((UINT32)PciConfigurationHeader.Bridge.P2PBridge.PrefetchableMemoryBase & 0xfff0) << 16;
Limit = (((UINT32)PciConfigurationHeader.Bridge.P2PBridge.PrefetchableMemoryLimit & 0xfff0) << 16) | 0xffffff;
if (Value == 0x01) {
Base |= LShiftU64((UINT64)PciConfigurationHeader.Bridge.P2PBridge.PrefetchableBaseUpper32,32);
Limit |= LShiftU64((UINT64)PciConfigurationHeader.Bridge.P2PBridge.PrefetchableLimitUpper32,32);
}
if (Base < Limit) {
if (PrivateData->MemBase > Base) {
PrivateData->MemBase = Base;
}
if (PrivateData->MemLimit < Limit) {
PrivateData->MemLimit = Limit;
}
if (Value == 0x00) {
if (PrivateData->Pmem32Base > Base) {
PrivateData->Pmem32Base = Base;
}
if (PrivateData->Pmem32Limit < Limit) {
PrivateData->Pmem32Limit = Limit;
}
}
if (Value == 0x01) {
if (PrivateData->Pmem64Base > Base) {
PrivateData->Pmem64Base = Base;
}
if (PrivateData->Pmem64Limit < Limit) {
PrivateData->Pmem64Limit = Limit;
}
}
}
//
// Look at the PPB Configuration for legacy decoding attributes
//
if (PciConfigurationHeader.Bridge.P2PBridge.BridgeControl & 0x04) {
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
}
if (PciConfigurationHeader.Bridge.P2PBridge.BridgeControl & 0x08) {
// PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
}
} else if (IS_CARDBUS_BRIDGE(&PciConfigurationHeader)) {
//
// Get the Bus range that the PPB is decoding
//
if (PciConfigurationHeader.Bridge.CardBridge.SubordinateBusNumber > PrivateData->SubordinateBus) {
//
// If the suborinate bus number of the PCI-PCI bridge is greater than the PCI root bridge's
// current subordinate bus number, then update the PCI root bridge's subordinate bus number
//
PrivateData->SubordinateBus = PciConfigurationHeader.Bridge.CardBridge.SubordinateBusNumber;
}
//
// Get the I/O range that the PPB is decoding
//
Base = PciConfigurationHeader.Bridge.CardBridge.IoBase0;
Limit = PciConfigurationHeader.Bridge.CardBridge.IoLimit0;
if (Base < Limit) {
if (PrivateData->IoBase > Base) {
PrivateData->IoBase = Base;
}
if (PrivateData->IoLimit < Limit) {
PrivateData->IoLimit = Limit;
}
}
//
// Get the Memory range that the PPB is decoding
//
Base = PciConfigurationHeader.Bridge.CardBridge.MemoryBase0;
Limit = PciConfigurationHeader.Bridge.CardBridge.MemoryLimit0;
if (Base < Limit) {
if (PrivateData->MemBase > Base) {
PrivateData->MemBase = Base;
}
if (PrivateData->MemLimit < Limit) {
PrivateData->MemLimit = Limit;
}
if (PrivateData->Mem32Base > Base) {
PrivateData->Mem32Base = Base;
}
if (PrivateData->Mem32Limit < Limit) {
PrivateData->Mem32Limit = Limit;
}
}
} else
{
//
// Parse the BARs of the PCI device to determine what I/O Ranges,
// Memory Ranges, and Prefetchable Memory Ranges the device is decoding
//
if ((PciConfigurationHeader.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {
Status = PcatPciRootBridgeParseBars (
PrivateData,
PciConfigurationHeader.Hdr.Command,
PrimaryBusIndex,
Device,
Function
);
}
//
// See if the PCI device is an IDE controller
//
if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x01 &&
PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ) {
if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x80) {
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x01) {
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
}
if (PciConfigurationHeader.Hdr.ClassCode[0] & 0x04) {
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
}
//
// See if the PCI device is a legacy VGA controller
//
if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x00 &&
PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ) {
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
}
//
// See if the PCI device is a standard VGA controller
//
if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x03 &&
PciConfigurationHeader.Hdr.ClassCode[1] == 0x00 ) {
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
}
//
// See if the PCI Device is a PCI - ISA or PCI - EISA
// or ISA_POSITIVIE_DECODE Bridge device
//
if (PciConfigurationHeader.Hdr.ClassCode[2] == 0x06) {
if (PciConfigurationHeader.Hdr.ClassCode[1] == 0x01 ||
PciConfigurationHeader.Hdr.ClassCode[1] == 0x02 ||
PciConfigurationHeader.Hdr.ClassCode[1] == 0x80 ) {
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
PrivateData->Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
if (PrivateData->MemBase > 0xa0000) {
PrivateData->MemBase = 0xa0000;
}
if (PrivateData->MemLimit < 0xbffff) {
PrivateData->MemLimit = 0xbffff;
}
}
}
}
//
// If this device is not a multi function device, then skip the rest of this PCI device
//
if (Function == 0 && !(PciConfigurationHeader.Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)) {
break;
}
}
}
//
// After scanning all the PCI devices on the PCI root bridge's primary bus, update the
// Primary Bus Number for the next PCI root bridge to be this PCI root bridge's subordinate
// bus number + 1.
//
PrimaryBusIndex = PrivateData->SubordinateBus + 1;
//
// If at least one PCI device was found on the primary bus of this PCI root bridge, then the PCI root bridge
// exists.
//
if (NumberOfPciDevices > 0) {
//
// Adjust the I/O range used for bounds checking for the legacy decoding attributed
//
if (PrivateData->Attributes & 0x7f) {
PrivateData->IoBase = 0;
if (PrivateData->IoLimit < 0xffff) {
PrivateData->IoLimit = 0xffff;
}
}
//
// Adjust the Memory range used for bounds checking for the legacy decoding attributed
//
if (PrivateData->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) {
if (PrivateData->MemBase > 0xa0000) {
PrivateData->MemBase = 0xa0000;
}
if (PrivateData->MemLimit < 0xbffff) {
PrivateData->MemLimit = 0xbffff;
}
}
//
// Build ACPI descriptors for the resources on the PCI Root Bridge
//
Status = ConstructConfiguration(PrivateData);
ASSERT_EFI_ERROR (Status);
//
// Create the handle for this PCI Root Bridge
//
Status = gBS->InstallMultipleProtocolInterfaces (
&PrivateData->Handle,
&gEfiDevicePathProtocolGuid,
PrivateData->DevicePath,
&gEfiPciRootBridgeIoProtocolGuid,
&PrivateData->Io,
NULL
);
ASSERT_EFI_ERROR (Status);
//
// Contruct DeviceIoProtocol
//
Status = DeviceIoConstructor (
PrivateData->Handle,
&PrivateData->Io,
PrivateData->DevicePath,
(UINT16)PrivateData->PrimaryBus,
(UINT16)PrivateData->SubordinateBus
);
ASSERT_EFI_ERROR (Status);
#if 0 //patch by nms42
//
// Scan this PCI Root Bridge for PCI Option ROMs and add them to the PCI Option ROM Table
//
Status = ScanPciRootBridgeForRoms(&PrivateData->Io);
#endif
//
// Increment the index for the next PCI Root Bridge
//
PciRootBridgeIndex++;
} else {
//
// If no PCI Root Bridges were found on the current PCI segment, then exit
//
if (NumberOfPciRootBridges == 0) {
Status = EFI_SUCCESS;
goto Done;
}
}
//
// If the PrimaryBusIndex is greater than the maximum allowable PCI bus number, then
// the PCI Segment Number is incremented, and the next segment is searched starting at Bus #0
// Otherwise, the search is continued on the next PCI Root Bridge
//
if (PrimaryBusIndex > PCI_MAX_BUS) {
PciSegmentIndex++;
NumberOfPciRootBridges = 0;
PrimaryBusIndex = 0;
} else {
NumberOfPciRootBridges++;
}
}
return EFI_SUCCESS;
Done:
//
// Clean up memory allocated for the PCI Root Bridge that was searched but not created.
//
if (PrivateData) {
if (PrivateData->DevicePath) {
gBS->FreePool(PrivateData->DevicePath);
}
gBS->FreePool (PrivateData);
}
//
// If no PCI Root Bridges were discovered, then return the error condition from scanning the
// first PCI Root Bridge
//
if (PciRootBridgeIndex == 0) {
return Status;
}
return EFI_SUCCESS;
}
VOID
CheckForRom (
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
UINT16 MinBus,
UINT16 MaxBus,
UINT16 MinDevice,
UINT16 MaxDevice,
UINT16 MinFunc,
UINT16 MaxFunc,
UINT16 Bus,
UINT16 Device,
UINT16 Func,
IN VOID *VoidContext
)
{
EFI_STATUS Status;
PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *Context;
UINT64 Address;
PCI_TYPE00 PciHeader;
PCI_TYPE01 *PciBridgeHeader;
UINT32 Register;
UINT32 RomBar;
UINT32 RomBarSize;
EFI_PHYSICAL_ADDRESS RomBuffer;
UINT32 MaxRomSize;
EFI_PCI_EXPANSION_ROM_HEADER EfiRomHeader;
PCI_DATA_STRUCTURE Pcir;
EFI_PCI_OPTION_ROM_DESCRIPTOR *TempPciOptionRomDescriptors;
BOOLEAN LastImage;
Context = (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *)VoidContext;
Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);
//
// Save the contents of the PCI Configuration Header
//
IoDev->Pci.Read (IoDev, EfiPciWidthUint32, Address, sizeof(PciHeader)/sizeof(UINT32), &PciHeader);
if (IS_PCI_BRIDGE(&PciHeader)) {
PciBridgeHeader = (PCI_TYPE01 *)(&PciHeader);
//
// See if the PCI-PCI Bridge has its secondary interface enabled.
//
if (PciBridgeHeader->Bridge.SubordinateBus >= PciBridgeHeader->Bridge.SecondaryBus) {
//
// Disable the Prefetchable Memory Window
//
Register = 0x00000000;
IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x26, 1, &Register);
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x2c, 1, &Register);
Register = 0xffffffff;
IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x24, 1, &Register);
IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x28, 1, &Register);
//
// Program Memory Window to the PCI Root Bridge Memory Window
//
IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x20, 4, &Context->PpbMemoryWindow);
//
// Enable the Memory decode for the PCI-PCI Bridge
//
IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
Register |= 0x02;
IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
//
// Recurse on the Secondary Bus Number
//
ScanPciBus(
IoDev,
PciBridgeHeader->Bridge.SecondaryBus, PciBridgeHeader->Bridge.SecondaryBus,
0, PCI_MAX_DEVICE,
0, PCI_MAX_FUNC,
CheckForRom, Context
);
}
} else {
//
// Check if an Option ROM Register is present and save the Option ROM Window Register
//
RomBar = 0xffffffff;
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
IoDev->Pci.Read (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
RomBarSize = (~(RomBar & 0xfffff800)) + 1;
//
// Make sure the size of the ROM is between 0 and 16 MB
//
if (RomBarSize > 0 && RomBarSize <= 0x01000000) {
//
// Program Option ROM Window Register to the PCI Root Bridge Window and Enable the Option ROM Window
//
RomBar = (Context->PpbMemoryWindow & 0xffff) << 16;
RomBar = ((RomBar - 1) & (~(RomBarSize - 1))) + RomBarSize;
if (RomBar < (Context->PpbMemoryWindow & 0xffff0000)) {
MaxRomSize = (Context->PpbMemoryWindow & 0xffff0000) - RomBar;
RomBar = RomBar + 1;
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
IoDev->Pci.Read (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
RomBar = RomBar - 1;
//
// Enable the Memory decode for the PCI Device
//
IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
Register |= 0x02;
IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
//
// Follow the chain of images to determine the size of the Option ROM present
// Keep going until the last image is found by looking at the Indicator field
// or the size of an image is 0, or the size of all the images is bigger than the
// size of the window programmed into the PPB.
//
RomBarSize = 0;
do {
LastImage = TRUE;
ZeroMem (&EfiRomHeader, sizeof(EfiRomHeader));
IoDev->Mem.Read (
IoDev,
EfiPciWidthUint8,
RomBar + RomBarSize,
sizeof(EfiRomHeader),
&EfiRomHeader
);
Pcir.ImageLength = 0;
if (EfiRomHeader.Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE &&
EfiRomHeader.PcirOffset != 0 &&
(EfiRomHeader.PcirOffset & 3) == 0 &&
RomBarSize + EfiRomHeader.PcirOffset + sizeof (PCI_DATA_STRUCTURE) <= MaxRomSize) {
ZeroMem (&Pcir, sizeof(Pcir));
IoDev->Mem.Read (
IoDev,
EfiPciWidthUint8,
RomBar + RomBarSize + EfiRomHeader.PcirOffset,
sizeof(Pcir),
&Pcir
);
if (Pcir.Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
break;
}
if (RomBarSize + Pcir.ImageLength * 512 > MaxRomSize) {
break;
}
if ((Pcir.Indicator & 0x80) == 0x00) {
LastImage = FALSE;
}
RomBarSize += Pcir.ImageLength * 512;
}
} while (!LastImage && RomBarSize < MaxRomSize && Pcir.ImageLength !=0);
if (RomBarSize > 0) {
//
// Allocate a memory buffer for the Option ROM contents.
//
Status = gBS->AllocatePages(
AllocateAnyPages,
EfiBootServicesData,
EFI_SIZE_TO_PAGES(RomBarSize),
&RomBuffer
);
if (!EFI_ERROR (Status)) {
//
// Copy the contents of the Option ROM to the memory buffer
//
IoDev->Mem.Read (IoDev, EfiPciWidthUint32, RomBar, RomBarSize / sizeof(UINT32), (VOID *)(UINTN)RomBuffer);
Status = gBS->AllocatePool(
EfiBootServicesData,
((UINT32)mPciOptionRomTable.PciOptionRomCount + 1) * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR),
(VOID*)&TempPciOptionRomDescriptors
);
if (mPciOptionRomTable.PciOptionRomCount > 0) {
CopyMem(
TempPciOptionRomDescriptors,
mPciOptionRomTable.PciOptionRomDescriptors,
(UINT32)mPciOptionRomTable.PciOptionRomCount * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR)
);
gBS->FreePool(mPciOptionRomTable.PciOptionRomDescriptors);
}
mPciOptionRomTable.PciOptionRomDescriptors = TempPciOptionRomDescriptors;
TempPciOptionRomDescriptors = &(mPciOptionRomTable.PciOptionRomDescriptors[(UINT32)mPciOptionRomTable.PciOptionRomCount]);
TempPciOptionRomDescriptors->RomAddress = RomBuffer;
TempPciOptionRomDescriptors->MemoryType = EfiBootServicesData;
TempPciOptionRomDescriptors->RomLength = RomBarSize;
TempPciOptionRomDescriptors->Seg = (UINT32)IoDev->SegmentNumber;
TempPciOptionRomDescriptors->Bus = (UINT8)Bus;
TempPciOptionRomDescriptors->Dev = (UINT8)Device;
TempPciOptionRomDescriptors->Func = (UINT8)Func;
TempPciOptionRomDescriptors->ExecutedLegacyBiosImage = TRUE;
TempPciOptionRomDescriptors->DontLoadEfiRom = FALSE;
mPciOptionRomTable.PciOptionRomCount++;
}
}
//
// Disable the Memory decode for the PCI-PCI Bridge
//
IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
Register &= (~0x02);
IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
}
}
}
//
// Restore the PCI Configuration Header
//
IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address, sizeof(PciHeader)/sizeof(UINT32), &PciHeader);
}
/**
Dump the resource map of all the devices under Bridge.
@param[in] Bridge Bridge device instance.
@param[in] IoNode IO resource descriptor for the bridge device.
@param[in] Mem32Node Mem32 resource descriptor for the bridge device.
@param[in] PMem32Node PMem32 resource descriptor for the bridge device.
@param[in] Mem64Node Mem64 resource descriptor for the bridge device.
@param[in] PMem64Node PMem64 resource descriptor for the bridge device.
**/
VOID
DumpResourceMap (
IN PCI_IO_DEVICE *Bridge,
IN PCI_RESOURCE_NODE *IoNode,
IN PCI_RESOURCE_NODE *Mem32Node,
IN PCI_RESOURCE_NODE *PMem32Node,
IN PCI_RESOURCE_NODE *Mem64Node,
IN PCI_RESOURCE_NODE *PMem64Node
)
{
EFI_STATUS Status;
LIST_ENTRY *Link;
PCI_IO_DEVICE *Device;
PCI_RESOURCE_NODE *ChildIoNode;
PCI_RESOURCE_NODE *ChildMem32Node;
PCI_RESOURCE_NODE *ChildPMem32Node;
PCI_RESOURCE_NODE *ChildMem64Node;
PCI_RESOURCE_NODE *ChildPMem64Node;
CHAR16 *Str;
DEBUG ((EFI_D_INFO, "PciBus: Resource Map for "));
Status = gBS->OpenProtocol (
Bridge->Handle,
&gEfiPciRootBridgeIoProtocolGuid,
NULL,
NULL,
NULL,
EFI_OPEN_PROTOCOL_TEST_PROTOCOL
);
if (EFI_ERROR (Status)) {
DEBUG ((
EFI_D_INFO, "Bridge [%02x|%02x|%02x]\n",
Bridge->BusNumber, Bridge->DeviceNumber, Bridge->FunctionNumber
));
} else {
Str = ConvertDevicePathToText (
DevicePathFromHandle (Bridge->Handle),
FALSE,
FALSE
);
DEBUG ((EFI_D_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));
if (Str != NULL) {
FreePool (Str);
}
}
DumpBridgeResource (IoNode);
DumpBridgeResource (Mem32Node);
DumpBridgeResource (PMem32Node);
DumpBridgeResource (Mem64Node);
DumpBridgeResource (PMem64Node);
DEBUG ((EFI_D_INFO, "\n"));
for ( Link = Bridge->ChildList.ForwardLink
; Link != &Bridge->ChildList
; Link = Link->ForwardLink
) {
Device = PCI_IO_DEVICE_FROM_LINK (Link);
if (IS_PCI_BRIDGE (&Device->Pci)) {
ChildIoNode = (IoNode == NULL ? NULL : FindResourceNode (Device, IoNode));
ChildMem32Node = (Mem32Node == NULL ? NULL : FindResourceNode (Device, Mem32Node));
ChildPMem32Node = (PMem32Node == NULL ? NULL : FindResourceNode (Device, PMem32Node));
ChildMem64Node = (Mem64Node == NULL ? NULL : FindResourceNode (Device, Mem64Node));
ChildPMem64Node = (PMem64Node == NULL ? NULL : FindResourceNode (Device, PMem64Node));
DumpResourceMap (
Device,
ChildIoNode,
ChildMem32Node,
ChildPMem32Node,
ChildMem64Node,
ChildPMem64Node
);
}
}
}
/**
Scan for all root bridges in platform.
@param[out] NumberOfRootBridges Number of root bridges detected
@retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
**/
PCI_ROOT_BRIDGE *
ScanForRootBridges (
OUT UINTN *NumberOfRootBridges
)
{
UINTN PrimaryBus;
UINTN SubBus;
UINT8 Device;
UINT8 Function;
UINTN NumberOfDevices;
UINTN Address;
PCI_TYPE01 Pci;
UINT64 Attributes;
UINT64 Base;
UINT64 Limit;
UINT64 Value;
PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;
PCI_ROOT_BRIDGE *RootBridges;
UINTN BarOffsetEnd;
*NumberOfRootBridges = 0;
RootBridges = NULL;
//
// After scanning all the PCI devices on the PCI root bridge's primary bus,
// update the Primary Bus Number for the next PCI root bridge to be this PCI
// root bridge's subordinate bus number + 1.
//
for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
SubBus = PrimaryBus;
Attributes = 0;
Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;
//
// Scan all the PCI devices on the primary bus of the PCI root bridge
//
for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
//
// Compute the PCI configuration address of the PCI device to probe
//
Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);
//
// Read the Vendor ID from the PCI Configuration Header
//
if (PciRead16 (Address) == MAX_UINT16) {
if (Function == 0) {
//
// If the PCI Configuration Read fails, or a PCI device does not
// exist, then skip this entire PCI device
//
break;
} else {
//
// If PCI function != 0, VendorId == 0xFFFF, we continue to search
// PCI function.
//
continue;
}
}
//
// Read the entire PCI Configuration Header
//
PciReadBuffer (Address, sizeof (Pci), &Pci);
//
// Increment the number of PCI device found on the primary bus of the
// PCI root bridge
//
NumberOfDevices++;
//
// Look for devices with the VGA Palette Snoop enabled in the COMMAND
// register of the PCI Config Header
//
if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
}
BarOffsetEnd = 0;
//
// PCI-PCI Bridge
//
if (IS_PCI_BRIDGE (&Pci)) {
//
// Get the Bus range that the PPB is decoding
//
if (Pci.Bridge.SubordinateBus > SubBus) {
//
// If the suborinate bus number of the PCI-PCI bridge is greater
// than the PCI root bridge's current subordinate bus number,
// then update the PCI root bridge's subordinate bus number
//
SubBus = Pci.Bridge.SubordinateBus;
}
//
// Get the I/O range that the PPB is decoding
//
Value = Pci.Bridge.IoBase & 0x0f;
Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
if (Value == BIT0) {
Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);
Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);
}
if ((Base > 0) && (Base < Limit)) {
if (Io.Base > Base) {
Io.Base = Base;
}
if (Io.Limit < Limit) {
Io.Limit = Limit;
}
}
//
// Get the Memory range that the PPB is decoding
//
Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;
Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
if ((Base > 0) && (Base < Limit)) {
if (Mem.Base > Base) {
Mem.Base = Base;
}
if (Mem.Limit < Limit) {
Mem.Limit = Limit;
}
}
//
// Get the Prefetchable Memory range that the PPB is decoding
//
Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;
Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
<< 16) | 0xfffff;
MemAperture = &PMem;
if (Value == BIT0) {
Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
MemAperture = &PMemAbove4G;
}
if ((Base > 0) && (Base < Limit)) {
if (MemAperture->Base > Base) {
MemAperture->Base = Base;
}
if (MemAperture->Limit < Limit) {
MemAperture->Limit = Limit;
}
}
//
// Look at the PPB Configuration for legacy decoding attributes
//
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)
== EFI_PCI_BRIDGE_CONTROL_ISA) {
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
}
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)
== EFI_PCI_BRIDGE_CONTROL_VGA) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)
!= 0) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
}
}
BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);
} else {
//
// Parse the BARs of the PCI device to get what I/O Ranges, Memory
// Ranges, and Prefetchable Memory Ranges the device is decoding
//
if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {
BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);
}
}
PcatPciRootBridgeParseBars (
Pci.Hdr.Command,
PrimaryBus,
Device,
Function,
OFFSET_OF (PCI_TYPE00, Device.Bar),
BarOffsetEnd,
&Io,
&Mem, &MemAbove4G,
&PMem, &PMemAbove4G
);
//
// See if the PCI device is an IDE controller
//
if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,
PCI_CLASS_MASS_STORAGE_IDE)) {
if (Pci.Hdr.ClassCode[0] & 0x80) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
if (Pci.Hdr.ClassCode[0] & 0x01) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
}
if (Pci.Hdr.ClassCode[0] & 0x04) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
}
//
// See if the PCI device is a legacy VGA controller or
// a standard VGA controller
//
if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||
IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)
) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
}
//
// See if the PCI Device is a PCI - ISA or PCI - EISA
// or ISA_POSITIVIE_DECODE Bridge device
//
if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
}
}
//
// If this device is not a multi function device, then skip the rest
// of this PCI device
//
if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
break;
}
}
}
//
// If at least one PCI device was found on the primary bus of this PCI
// root bridge, then the PCI root bridge exists.
//
if (NumberOfDevices > 0) {
RootBridges = ReallocatePool (
(*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),
(*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),
RootBridges
);
ASSERT (RootBridges != NULL);
AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);
InitRootBridge (
Attributes, Attributes, 0,
(UINT8) PrimaryBus, (UINT8) SubBus,
&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,
&RootBridges[*NumberOfRootBridges]
);
RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;
//
// Increment the index for the next PCI Root Bridge
//
(*NumberOfRootBridges)++;
}
}
return RootBridges;
}