/*
========================================================================
Routine Description:
Initialize chip related information.
Arguments:
pCB - WLAN control block pointer
Return Value:
None
Note:
========================================================================
*/
int RtmpChipOpsHook(VOID *pCB)
{
RTMP_ADAPTER *pAd = (RTMP_ADAPTER *)pCB;
RTMP_CHIP_CAP *pChipCap = &pAd->chipCap;
UINT32 MacValue;
int ret = 0;
RTMP_CHIP_OP *pChipOps = &pAd->chipOps;
/* sanity check */
if (WaitForAsicReady(pAd) == FALSE)
return -1;
// TODO: shiang-7603
if (IS_MT7603(pAd) || IS_MT7628(pAd) || IS_MT76x6(pAd)) {
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_OFF, ("%s(%d): Not support for HIF_MT yet!\n",
__FUNCTION__, __LINE__));
}
else
{
#if defined(RTMP_MAC) || defined(RLT_MAC)
RTMP_IO_READ32(pAd, MAC_CSR0, &MacValue);
pAd->MACVersion = MacValue;
#endif /* defined(RTMP_MAC) || defined(RLT_MAC) */
}
if (pAd->MACVersion == 0xffffffff)
return -1;
/* default init */
RTMP_DRS_ALG_INIT(pAd, RATE_ALG_LEGACY);
#ifdef RTMP_RBUS_SUPPORT
if (pAd->infType == RTMP_DEV_INF_RBUS)
{
RTMP_SYS_IO_READ32(0xb000000c, &pAd->CommonCfg.CID);
RTMP_SYS_IO_READ32(0xb0000000, &pAd->CommonCfg.CN);
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_TRACE, ("CN: %lx\tCID = %lx\n",
pAd->CommonCfg.CN, pAd->CommonCfg.CID));
}
#endif /* RTMP_RBUS_SUPPORT */
/* EDCCA */
pChipOps->ChipSetEDCCA= NULL;
#ifdef MT7628
if (IS_MT7628(pAd)) {
mt7628_init(pAd);
goto done;
}
#endif /* MT7628 */
#ifdef MT7615
if (IS_MT7615(pAd)) {
mt7615_init(pAd);
goto done;
};
#endif /* MT7615 */
#ifdef GREENAP_SUPPORT
pChipOps->EnableAPMIMOPS = EnableAPMIMOPSv1;
pChipOps->DisableAPMIMOPS = DisableAPMIMOPSv1;
#endif /* GREENAP_SUPPORT */
#ifdef RTMP_MAC
// TODO: default settings for rest of the chips!! change this to really default chip.
RTxx_default_Init(pAd);
#endif /* RTMP_MAC */
/* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
#ifdef RT305x
#ifdef RT3352
/*FIXME by Steven: RFIC=RFIC_3022 in some RT3352 board*/
/* if (pAd->RfIcType == RFIC_3322) {*/
if (IS_RT3352(pAd))
RT3352_Init(pAd);
else
#endif /* RT3352 */
#ifdef RT5350
if (IS_RT5350(pAd))
RT5350_Init(pAd);
else
#endif /* RT5350 */
/* comment : the RfIcType is not ready yet, because EEPROM doesn't be initialized. */
/* if ((pAd->MACVersion == 0x28720200) &&
((pAd->RfIcType == RFIC_3320) || (pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022))) */
if (IS_RT3050_3052_3350(pAd))
RT305x_Init(pAd);
else
#endif /* RT305x */
done:
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipCap->bbpRegTbSize));
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_TRACE, ("Chip VCO calibration mode = %d!\n", pChipCap->FlgIsVcoReCalMode));
return ret;
}
VOID RT30xxATEAsicSwitchChannel(
IN PRTMP_ADAPTER pAd)
{
CHAR TxPwer = 0, TxPwer2 = 0;
UCHAR index = 0, Channel = 0;
UINT32 Value = 0;
#ifdef A_BAND_SUPPORT
UCHAR BbpValue = 0;
#endif /* A_BAND_SUPPORT */
#ifdef RTMP_RF_RW_SUPPORT
/* Added to prevent RF register reading error */
UCHAR RFValue = 0;
#endif /* RTMP_RF_RW_SUPPORT */
#ifdef RALINK_QA
/* For QA mode, TX power values are passed from UI */
if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
{
if (pAd->ate.Channel != pAd->LatchRfRegs.Channel)
{
pAd->ate.Channel = pAd->LatchRfRegs.Channel;
}
return;
}
else
#endif /* RALINK_QA */
Channel = pAd->ate.Channel;
/* Fill Tx power value */
TxPwer = pAd->ate.TxPower0;
TxPwer2 = pAd->ate.TxPower1;
/*
The RF programming sequence is difference between 3xxx and 2xxx.
The 3070 is 1T1R. Therefore, we don't need to set the number of Tx/Rx path
and the only job is to set the parameters of channels.
*/
if ((IS_RT30xx(pAd)) &&
((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
(pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320)))
{
for (index = 0; index < NUM_OF_3020_CHNL; index++)
{
if (Channel == FreqItems3020[index].Channel)
{
/* Programming channel parameters. */
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R02, FreqItems3020[index].N);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R03, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K&(~0xF0));
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R03, (UCHAR)RFValue);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R06, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R06, (UCHAR)RFValue);
/* Set Tx Power. */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R12, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xE0) | TxPwer;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R12, (UCHAR)RFValue);
/* Set RF offset. */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R23, (PUCHAR)&RFValue);
RFValue = (RFValue & 0x80) | pAd->ate.RFFreqOffset;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R23, (UCHAR)RFValue);
/* Set BW. */
if (pAd->ate.TxWI.BW == BW_40)
{
RFValue = pAd->Mlme.CaliBW40RfR24;
}
else
{
RFValue = pAd->Mlme.CaliBW20RfR24;
}
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR)RFValue);
/* Enable RF tuning */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R07, (PUCHAR)&RFValue);
RFValue = RFValue | 0x1;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R07, (UCHAR)RFValue);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
/* Latch channel for future usage */
pAd->LatchRfRegs.Channel = Channel;
ATEAsicSetTxRxPath(pAd);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
break;
}
}
DBGPRINT(RT_DEBUG_TRACE, ("%s::SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
__FUNCTION__,
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3020[index].N,
FreqItems3020[index].K,
FreqItems3020[index].R));
}
/* Change BBP setting during switch from a->g, g->a */
if (Channel <= 14)
{
UINT32 TxPinCfg = 0x00050F0A; /* 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
if (IS_RT3352(pAd) || IS_RT5350(pAd))
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x38);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
}
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForG)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 2.4 G band selection PIN */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
/* Calibration power unbalance issues */
if (pAd->Antenna.field.TxPath == 2)
{
if (pAd->ate.TxAntennaSel == 1)
{
TxPinCfg &= 0xFFFFFFF7;
}
else if (pAd->ate.TxAntennaSel == 2)
{
TxPinCfg &= 0xFFFFFFFD;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
#ifdef A_BAND_SUPPORT
else
{
UINT32 TxPinCfg = 0x00050F05; /* 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForA)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
ASSERT((BbpValue == 0x04));
/* 5 G band selection PIN, bit1 and bit2 are complement */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
#endif /* A_BAND_SUPPORT */
ATE_CHIP_RX_VGA_GAIN_INIT(pAd);
RtmpOsMsDelay(1);
#ifndef RTMP_RF_RW_SUPPORT
if (Channel <= 14)
{
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(pAd->LatchRfRegs.R3 & 0x00003e00) >> 9,
(pAd->LatchRfRegs.R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
