/*
* ターゲットシステム依存の初期化
*/
void
sys_initialize()
{
/*
* PLLの設定
*
*/
/*
* SSELVAL, CSELVALはboard_config.hにて定義。
*/
#ifndef FORCE_PLL_INITIALIZE
// PLLが初期値のままであり、かつ、SDRAMが利用中でなければPLLを初期化する
if ( ( *pPLL_CTL == 0x1400 ) && ( !(*pEBIU_SDBCTL & EBE ) ) )
#endif
{
*pSIC_IWR = IWR_ENABLE(0); // PLLのみIWRを許す
#if CSELVAL == 1
*pPLL_DIV = CSEL_DIV1 | SET_SSEL(SSELVAL);
#elif CSELVAL == 2
*pPLL_DIV = CSEL_DIV2 | SET_SSEL(SSELVAL);
#elif CSELVAL == 4
*pPLL_DIV = CSEL_DIV4 | SET_SSEL(SSELVAL);
#elif CSELVAL == 8
*pPLL_DIV = CSEL_DIV8 | SET_SSEL(SSELVAL);
#else
#error Wrong CSELVAL. Must be one of 1,2,4,8.
#endif
*pPLL_CTL = MSELVAL << 9;
asm("cli r0; csync; idle; sti r0;": : :"R0");
*pSIC_IWR = IWR_ENABLE_ALL;
}
/*
* ターゲットシステム依存の初期化
*/
void
sys_initialize()
{
/*
* スプリアス割り込みハンドラの設定
*
* cpu_initialize()が行うダミーの割り込みハンドラの設定を上書きする。
* アプリケーションが割り込みハンドラを設定すると、以下の設定も上書き
* される。
*/
int i;
for ( i=0; i<DEVICE_INTERRUPT_COUNT+3; i++ )
dev_vector[i] = &spurious_int_handler;
exc_vector = &spurious_exc_handler;
/*
* PLLの設定
*
*/
/*
* SSELVAL, CSELVALはboard_config.hにて定義。FORCE_PLL_INITIALIZEはsys_config.hで
* 必要に応じて宣言する。
*/
#ifndef FORCE_PLL_INITIALIZE
// PLLが初期値のままであり、かつ、SDRAMが利用中でなければPLLを初期化する
if ( ( *pPLL_CTL == 0x1400 ) && ( !(*pEBIU_SDBCTL & EBE ) ) )
#endif
{
*pSIC_IWR = IWR_ENABLE(0); // PLLのみIWRを許す
#if CSELVAL == 1
*pPLL_DIV = CSEL_DIV1 | SET_SSEL(SSELVAL);
#elif CSELVAL == 2
*pPLL_DIV = CSEL_DIV2 | SET_SSEL(SSELVAL);
#elif CSELVAL == 4
*pPLL_DIV = CSEL_DIV4 | SET_SSEL(SSELVAL);
#elif CSELVAL == 8
*pPLL_DIV = CSEL_DIV8 | SET_SSEL(SSELVAL);
#else
#error Wrong CSELVAL. Must be one of 1,2,4,8.
#endif
// PLLの分周器に値を設定する
*pPLL_CTL = MSELVAL << 9;
// PLLを起動する。
asm("cli r0; csync; idle; sti r0;": : :"R0");
*pSIC_IWR = IWR_ENABLE_ALL;
}
void init_clocks(void)
{
/* Kill any active DMAs as they may trigger external memory accesses
* in the middle of reprogramming things, and that'll screw us up.
* For example, any automatic DMAs left by U-Boot for splash screens.
*/
size_t i;
for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
struct dma_register *dma = dma_io_base_addr[i];
dma->cfg = 0;
}
do_sync();
#ifdef SIC_IWR0
bfin_write_SIC_IWR0(IWR_ENABLE(0));
# ifdef SIC_IWR1
/* BF52x system reset does not properly reset SIC_IWR1 which
* will screw up the bootrom as it relies on MDMA0/1 waking it
* up from IDLE instructions. See this report for more info:
* http://blackfin.uclinux.org/gf/tracker/4323
*/
if (ANOMALY_05000435)
bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
else
bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
# endif
# ifdef SIC_IWR2
bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
# endif
#else
bfin_write_SIC_IWR(IWR_ENABLE(0));
#endif
do_sync();
#ifdef EBIU_SDGCTL
bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
do_sync();
#endif
#ifdef CLKBUFOE
bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
do_sync();
__asm__ __volatile__("IDLE;");
#endif
bfin_write_PLL_LOCKCNT(0x300);
do_sync();
bfin_write16(PLL_CTL, PLL_CTL_VAL);
__asm__ __volatile__("IDLE;");
bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
#ifdef EBIU_SDGCTL
bfin_write_EBIU_SDRRC(mem_SDRRC);
bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
#else
bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
do_sync();
bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
#ifdef CONFIG_MEM_EBIU_DDRQUE
bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
#endif
#endif
do_sync();
bfin_read16(0);
}
