/** * ixgbevf_hv_set_rlpml_vf - Set the maximum receive packet length * @hw: pointer to the HW structure * @max_size: value to assign to max frame size * Hyper-V variant. **/ s32 ixgbevf_hv_set_rlpml_vf(struct ixgbe_hw *hw, u16 max_size) { u32 reg; /* If we are on Hyper-V, we implement this functionality * differently. */ reg = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(0)); /* CRC == 4 */ reg |= ((max_size + 4) | IXGBE_RXDCTL_RLPML_EN); IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(0), reg); return IXGBE_SUCCESS; }
static void ixgbevf_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) { struct ixgbevf_adapter *adapter = netdev_priv(netdev); struct ixgbe_hw *hw = &adapter->hw; u32 *regs_buff = p; u32 regs_len = ixgbevf_get_regs_len(netdev); u8 i; memset(p, 0, regs_len); regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id; /* General Registers */ regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_VFCTRL); regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_VFSTATUS); regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_VFLINKS); regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_VFRXMEMWRAP); regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_VFFRTIMER); /* Interrupt */ /* don't read EICR because it can clear interrupt causes, instead * read EICS which is a shadow but doesn't clear EICR */ regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_VTEICS); regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_VTEICS); regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_VTEIMS); regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_VTEIMC); regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_VTEIAC); regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_VTEIAM); regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_VTEITR(0)); regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_VTIVAR(0)); regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); /* Receive DMA */ for (i = 0; i < 2; i++) regs_buff[14 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAL(i)); for (i = 0; i < 2; i++) regs_buff[16 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAH(i)); for (i = 0; i < 2; i++) regs_buff[18 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDLEN(i)); for (i = 0; i < 2; i++) regs_buff[20 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDH(i)); for (i = 0; i < 2; i++) regs_buff[22 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDT(i)); for (i = 0; i < 2; i++) regs_buff[24 + i] = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i)); for (i = 0; i < 2; i++) regs_buff[26 + i] = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(i)); /* Receive */ regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_VFPSRTYPE); /* Transmit */ for (i = 0; i < 2; i++) regs_buff[29 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDBAL(i)); for (i = 0; i < 2; i++) regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDBAH(i)); for (i = 0; i < 2; i++) regs_buff[33 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDLEN(i)); for (i = 0; i < 2; i++) regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDH(i)); for (i = 0; i < 2; i++) regs_buff[37 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDT(i)); for (i = 0; i < 2; i++) regs_buff[39 + i] = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i)); for (i = 0; i < 2; i++) regs_buff[41 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDWBAL(i)); for (i = 0; i < 2; i++) regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDWBAH(i)); for (i = 0; i < ARRAY_SIZE(ixgbevf_reg_names); i++) hw_dbg(hw, "%s\t%8.8x\n", ixgbevf_reg_names[i], regs_buff[i]); }
* registers to be written without any read-back testing. */ #define PATTERN_TEST 1 #define SET_READ_TEST 2 #define WRITE_NO_TEST 3 #define TABLE32_TEST 4 #define TABLE64_TEST_LO 5 #define TABLE64_TEST_HI 6 /* default VF register test */ static const struct ixgbevf_reg_test reg_test_vf[] = { { IXGBE_VFRDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, { IXGBE_VFRDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, { IXGBE_VFRDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, { IXGBE_VFRXDCTL(0), 2, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, { IXGBE_VFRDT(0), 2, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, { IXGBE_VFRXDCTL(0), 2, WRITE_NO_TEST, 0, 0 }, { IXGBE_VFTDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, { IXGBE_VFTDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, { IXGBE_VFTDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, { 0, 0, 0, 0 } }; static const u32 register_test_patterns[] = { 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF }; #define REG_PATTERN_TEST(R, M, W) \ { \ u32 pat, val, before; \
static void ixgbevf_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) { struct ixgbevf_adapter *adapter = netdev_priv(netdev); struct ixgbe_hw *hw = &adapter->hw; u32 *regs_buff = p; u32 regs_len = ixgbevf_get_regs_len(netdev); u8 i; memset(p, 0, regs_len); regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id; regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_VFCTRL); regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_VFSTATUS); regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_VFLINKS); regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_VFRXMEMWRAP); regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_VFFRTIMER); regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_VTEICS); regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_VTEICS); regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_VTEIMS); regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_VTEIMC); regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_VTEIAC); regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_VTEIAM); regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_VTEITR(0)); regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_VTIVAR(0)); regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); for (i = 0; i < 2; i++) regs_buff[14 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAL(i)); for (i = 0; i < 2; i++) regs_buff[16 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAH(i)); for (i = 0; i < 2; i++) regs_buff[18 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDLEN(i)); for (i = 0; i < 2; i++) regs_buff[20 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDH(i)); for (i = 0; i < 2; i++) regs_buff[22 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDT(i)); for (i = 0; i < 2; i++) regs_buff[24 + i] = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i)); for (i = 0; i < 2; i++) regs_buff[26 + i] = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(i)); regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_VFPSRTYPE); for (i = 0; i < 2; i++) regs_buff[29 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDBAL(i)); for (i = 0; i < 2; i++) regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDBAH(i)); for (i = 0; i < 2; i++) regs_buff[33 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDLEN(i)); for (i = 0; i < 2; i++) regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDH(i)); for (i = 0; i < 2; i++) regs_buff[37 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDT(i)); for (i = 0; i < 2; i++) regs_buff[39 + i] = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i)); for (i = 0; i < 2; i++) regs_buff[41 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDWBAL(i)); for (i = 0; i < 2; i++) regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDWBAH(i)); for (i = 0; i < ARRAY_SIZE(ixgbevf_reg_names); i++) hw_dbg(hw, "%s\t%8.8x\n", ixgbevf_reg_names[i], regs_buff[i]); }