IX_STATUS ixParityENAccPbcPEParityInterruptClear ( IxParityENAccPbcPEParityErrorContext ixPbcPECMsg) { IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, "\nixParityENAccPbcPEParityInterruptClear():" "\n\tpbcParitySource:%x\tpbcAccessType:%x\n", ixPbcPECMsg.pbcParitySource,ixPbcPECMsg.pbcAccessType,0,0,0,0); IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_DEBUG2, IX_OSAL_LOG_DEV_STDOUT, "ixParityENAccPbcPEParityInterruptClear(): " "\nIXP400_PARITYENACC_PE_PBC_INITIATOR:%x" "\tIXP400_PARITYENACC_PE_READ:%x\n", (IXP400_PARITYENACC_PE_PBC_INITIATOR),(IXP400_PARITYENACC_PE_READ),0,0,0,0); /* Clear off Parity Error Status due to PCI Initiator Read? */ if (IXP400_PARITYENACC_PE_PBC_INITIATOR == ixPbcPECMsg.pbcParitySource) { /* Write '1' to clear off the srcr.MDPE and srcr.DPE */ IXP400_PARITYENACC_VAL_BIT_SET( ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue, (IXP400_PARITYENACC_PBC_PCICFG_SRCR_MDPE | IXP400_PARITYENACC_PBC_PCICFG_SRCR_DPE) ); } /* end of if */ /* Clear off Parity Error Status due to PCI Target Write? */ if (IXP400_PARITYENACC_PE_PBC_TARGET == ixPbcPECMsg.pbcParitySource) { /* Write '1' to clear off the srcr.DPE */ IXP400_PARITYENACC_VAL_BIT_SET( ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue, IXP400_PARITYENACC_PBC_PCICFG_SRCR_DPE); } /* end of if */ /* Clear parity error interrupt status */ ixParityENAccPbcPEParityErrorStatusClear(); return IX_SUCCESS; } /* end of ixParityENAccPbcPEParityInterruptClear() function */
IX_STATUS ixParityENAccAqmPEDetectionConfigure (IxParityENAccAqmPEConfigOption ixAqmPDCfg) { UINT32 aqmPDCfgFlags = IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_ENABLE; UINT32 aqmPDCfgStatus = 0; UINT32 aqmTmpPDCfgStatus = 0; /* Enable parity error detection */ if (IXP400_PARITYENACC_PE_ENABLE == ixAqmPDCfg) { IXP400_PARITYENACC_VAL_BIT_SET(aqmPDCfgStatus, aqmPDCfgFlags); } else /* Disable parity error detection */ { IXP400_PARITYENACC_VAL_BIT_CLEAR(aqmPDCfgStatus, aqmPDCfgFlags); } /* end of if */ /* * The following sequence of steps works without the following while loop on Emulator * but doesn't work on BMP */ while (TRUE != IXP400_PARITYENACC_VAL_BIT_CHECK(aqmTmpPDCfgStatus, aqmPDCfgStatus)) { /* Set the new configuration */ IXP400_PARITYENACC_REG_WRITE ( ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr, aqmPDCfgStatus); /* Verify that the configuration is successful or not */ IXP400_PARITYENACC_REG_READ( ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr,&aqmTmpPDCfgStatus); } if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(aqmTmpPDCfgStatus, aqmPDCfgStatus)) { return (IXP400_PARITYENACC_PE_ENABLE == ixAqmPDCfg) ? ixParityENAccIcInterruptEnable( IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT) : ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT); } else { return IX_FAIL; } /* end of if */ } /* end of ixParityENAccAqmPEDetectionConfigure() function */
IX_STATUS ixParityENAccEbcPEDetectionConfigure(IxParityENAccEbcPEConfigOption ixEbcPDCfg) { UINT32 ebcPDCfgFlags = 0; UINT32 ebcPDCfgStatus = 0; UINT32 ebcTmpPDCfgStatus = 0; register IxParityENAccEbcPERegisters *ebcPERegisters = &ixParityENAccEbcPEConfig.ebcPERegisters; int loopIdx = 100; if (IXP400_PARITYENACC_PE_EBC_CS == ixEbcPDCfg.ebcCsExtSource) { if (ixEbcPDCfg.ebcCsId >= IXP400_PARITYENACC_PE_EBC_CHIPSEL_MAX) { return IX_FAIL; } /* end of if */ /* Get current parity detection configuration of Chip Select */ IXP400_PARITYENACC_REG_READ( ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId], &ebcPDCfgStatus); /* Enable parity error detection */ ebcPDCfgFlags = IXP400_PARITYENACC_EBC_TIMING_CSX_PAR_EN; if (IXP400_PARITYENACC_PE_ENABLE == ixEbcPDCfg.ebcInOrOutbound.ebcCsEnabled) { IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus, ebcPDCfgFlags); } else /* Disable parity error detection */ { IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus, ebcPDCfgFlags); } /* end of if */ while (loopIdx-- && (ebcTmpPDCfgStatus != ebcPDCfgStatus)) { /* Set the new configuration */ IXP400_PARITYENACC_REG_WRITE( ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId], ebcPDCfgStatus); /* Configuration successful? */ IXP400_PARITYENACC_REG_READ( ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId],&ebcTmpPDCfgStatus); } if (ebcTmpPDCfgStatus != ebcPDCfgStatus) { return IX_FAIL; } /* end of if */ /* * This step required for Even/Odd Parity Type detection from the * EBC Master Control Register if the chip select configuration is * specified along with the parity type which is part of the Master * Control Register only */ /* Get current parity detection configuration of External Master */ IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl,&ebcPDCfgStatus); } /* else of if */ else /* EBC Master Control */ { ebcPDCfgFlags = IXP400_PARITYENACC_EBC_MST_CONTROL_INPAR_EN; /* Get current parity detection configuration */ IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl, &ebcPDCfgStatus); /* Enable parity error detection */ if (IXP400_PARITYENACC_PE_ENABLE == ixEbcPDCfg.ebcInOrOutbound.ebcExtMstEnabled) { IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus,ebcPDCfgFlags); } else /* Disable parity error detection */ { IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus,ebcPDCfgFlags); } /* end of if */ } /* end of if */ /* Set Even/Odd parity type */ ebcPDCfgFlags = IXP400_PARITYENACC_EBC_MST_CONTROL_ODDPARITY; if (IXP400_PARITYENACC_PE_ODD_PARITY == ixEbcPDCfg.parityOddEven) { IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus,ebcPDCfgFlags); } else /* Set even parity */ { IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus,ebcPDCfgFlags); } /* end of if */ loopIdx = 10; while (loopIdx-- && (ebcTmpPDCfgStatus != ebcPDCfgStatus)) { /* Set the new configuration */ IXP400_PARITYENACC_REG_WRITE(ebcPERegisters->expMstControl, ebcPDCfgStatus); /* Configuration successful? */ IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl,&ebcTmpPDCfgStatus); } if (ebcTmpPDCfgStatus == ebcPDCfgStatus) { /* Enable/Disable the corresponding interrupt at Interrupt Controller */ return ((IXP400_PARITYENACC_PE_ENABLE == ixEbcPDCfg.ebcInOrOutbound.ebcCsEnabled) || (IXP400_PARITYENACC_PE_ENABLE == ixEbcPDCfg.ebcInOrOutbound.ebcExtMstEnabled)) ? ixParityENAccIcInterruptEnable( IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT) : ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT); } else { IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccEbcPEDetectionConfigure(): returned IX_FAIL\n", 0,0,0,0,0,0); return IX_FAIL; } /* end of if */ } /* end of ixParityENAccEbcPEDetectionConfigure() function */
IX_STATUS ixParityENAccPbcPEDetectionConfigure(IxParityENAccPbcPEConfigOption ixPbcPDCfg) { UINT32 pbcPDCfgStatus = 0; UINT32 pbcTmpPDCfgStatus = 0; int loopIdx = 0; /* Read the PCI Controller PCI Config SRCR register */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ); IXP400_PARITYENACC_REG_READ( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata, &pbcPDCfgStatus); /* * Set/Clear the PER bit of SRCR register & * Enable/Disable Parity Error Notification */ if (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) { /* Set the PER bit of SRCR register */ IXP400_PARITYENACC_VAL_BIT_SET(pbcPDCfgStatus, IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER); /* Enable the PCI Parity Error Interrupt Notification */ IXP400_PARITYENACC_REG_BIT_SET( ixParityENAccPbcPEConfig.pbcPERegisters.pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE); } /* else of if */ else { /* Clear the PER bit of SRCR register */ IXP400_PARITYENACC_VAL_BIT_CLEAR(pbcPDCfgStatus, IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER); /* Disable the PCI Parity Error Interrupt Notification */ IXP400_PARITYENACC_REG_BIT_CLEAR( ixParityENAccPbcPEConfig.pbcPERegisters.pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE); } /* end of if */ /* Write back the PCI Controller PCI Config SRCR register */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_WRITE); IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpWdata, pbcPDCfgStatus); loopIdx = 10; while (loopIdx--) { /* Verify that the configuration is successful or not */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ); IXP400_PARITYENACC_REG_READ( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata, &pbcTmpPDCfgStatus); } if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(pbcPDCfgStatus, pbcTmpPDCfgStatus)) { /* Enable/Disable the corresponding interrupt at Interrupt Controller */ return (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) ? ixParityENAccIcInterruptEnable( IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT) : ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT); } else { return IX_FAIL; } /* end of if */ } /* end of ixParityENAccPbcPEDetectionConfigure() function */