/**Function*************************************************************
Synopsis [Interface with the FPGA mapping package.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void If_ManComputeSwitching( If_Man_t * pIfMan )
{
abctime clk = Abc_Clock();
Gia_Man_t * pNew;
Vec_Int_t * vCopy;
If_Obj_t * pIfObj;
int i;
assert( pIfMan->vSwitching == NULL );
// create the new manager
pNew = Gia_ManStart( If_ManObjNum(pIfMan) );
vCopy = Vec_IntAlloc( If_ManObjNum(pIfMan) );
// constant and inputs
Vec_IntPush( vCopy, 1 );
If_ManForEachCi( pIfMan, pIfObj, i )
Vec_IntPush( vCopy, Gia_ManAppendCi(pNew) );
// internal nodes
If_ManForEachNode( pIfMan, pIfObj, i )
{
int iLit0 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin0(pIfObj)->Id), If_ObjFaninC0(pIfObj) );
int iLit1 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin1(pIfObj)->Id), If_ObjFaninC1(pIfObj) );
Vec_IntPush( vCopy, Gia_ManAppendAnd(pNew, iLit0, iLit1) );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Nwk_Man_t * Nwk_ManFromIf( If_Man_t * pIfMan, Aig_Man_t * p, Vec_Ptr_t * vAigToIf )
{
Vec_Ptr_t * vIfToAig;
Nwk_Man_t * pNtk;
Nwk_Obj_t * pObjNew;
Aig_Obj_t * pObj, * pObjRepr;
If_Obj_t * pIfObj;
If_Cut_t * pCutBest;
int i, k, nLeaves, * ppLeaves;
assert( Aig_ManCiNum(p) == If_ManCiNum(pIfMan) );
assert( Aig_ManCoNum(p) == If_ManCoNum(pIfMan) );
assert( Aig_ManNodeNum(p) == If_ManAndNum(pIfMan) );
Aig_ManCleanData( p );
If_ManCleanCutData( pIfMan );
// create mapping of IF to AIG
vIfToAig = Vec_PtrStart( If_ManObjNum(pIfMan) );
Aig_ManForEachObj( p, pObj, i )
{
pIfObj = (If_Obj_t *)Vec_PtrEntry( vAigToIf, i );
Vec_PtrWriteEntry( vIfToAig, pIfObj->Id, pObj );
}
If_ManForEachCi( pIfMan, pIfObj, i )
Vec_IntPush( vCopy, Gia_ManAppendCi(pNew) );
// internal nodes
If_ManForEachNode( pIfMan, pIfObj, i )
{
int iLit0 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin0(pIfObj)->Id), If_ObjFaninC0(pIfObj) );
int iLit1 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin1(pIfObj)->Id), If_ObjFaninC1(pIfObj) );
Vec_IntPush( vCopy, Gia_ManAppendAnd(pNew, iLit0, iLit1) );
}
// outputs
If_ManForEachCo( pIfMan, pIfObj, i )
{
int iLit0 = Abc_LitNotCond( Vec_IntEntry(vCopy, If_ObjFanin0(pIfObj)->Id), If_ObjFaninC0(pIfObj) );
Vec_IntPush( vCopy, Gia_ManAppendCo(pNew, iLit0) );
}
assert( Vec_IntSize(vCopy) == If_ManObjNum(pIfMan) );
Vec_IntFree( vCopy );
// compute switching activity
pIfMan->vSwitching = Gia_ManComputeSwitchProbs( pNew, 48, 16, 0 );
Gia_ManStop( pNew );
if ( pIfMan->pPars->fVerbose )
Abc_PrintTime( 1, "Computing switching activity", Abc_Clock() - clk );
}
/**Function*************************************************************
Synopsis [Interface with the FPGA mapping package.]
Description []
SideEffects []
