void InitEPwmGpio(void)
{
#if DSP28_EPWM1
InitEPwm1Gpio();
#endif // endif DSP28_EPWM1
#if DSP28_EPWM2
InitEPwm2Gpio();
#endif // endif DSP28_EPWM2
#if DSP28_EPWM3
InitEPwm3Gpio();
#endif // endif DSP28_EPWM3
#if DSP28_EPWM4
InitEPwm4Gpio();
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
InitEPwm5Gpio();
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
InitEPwm6Gpio();
#endif // endif DSP28_EPWM6
#if DSP28_EPWM7
InitEPwm7Gpio();
#endif // endif DSP28_EPWM7
#if DSP28_EPWM8
InitEPwm8Gpio();
#endif // endif DSP28_EPWM8
}
void InitEPwmGpio(void)
{
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
}
void InitEPwmGpio(void)
{
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
#if DSP28_EPWM5
InitEPwm5Gpio();
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
InitEPwm6Gpio();
#endif // endif DSP28_EPWM6
}
//----------------------------------------------------------------------------------------------------------------------
void InitEPwm5(void){
InitEPwm5Gpio();
//EPWM 5 Configurations
EPwm5Regs.TBPRD = 2275; // 20 kHz
EPwm5Regs.TBPHS.half.TBPHS = 0x0000; // set phase to zero
EPwm5Regs.TBCTR = 0x0000; // Clear time base counter
//EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set shadow mode
//EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Set PWM5 to master
EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Set PWM5 to master
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
//EPwm5Regs.TBCTL.bit.PHSDIR = 1; // Count up after synch event
EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm5Regs.CMPA.half.CMPA = 2275; // the period
EPwm5Regs.CMPB = 2275;
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
EPwm5Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm5Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
EPwm5Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
EPwm5Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
EPwm5Regs.AQCTLB.bit.CBU = AQ_CLEAR;
EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm5Regs.ETSEL.bit.INTEN = PWM5_INT_ENABLE; // Enable INT
EPwm5Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm5Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm5Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from CMPA on upcount
EPwm5Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
/*// Active high complementary PWMs - Setup the deadband
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
//EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;
//EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm5Regs.DBCTL.bit.IN_MODE = DBB_RED_DBA_FED;
EPwm5Regs.DBRED = EPWM5_MIN_DB;
EPwm5Regs.DBFED = EPWM5_MIN_DB;
EPwm5_DB_Direction = DB_DOWN;*/
}
void pwm_config(void)
{
pwm_output_disable();
Periodo_ticks = pwm_period_calculation(F_SAMP);
pwm1_config(); //pulsos disparo
pwm2_config(); //pulsos disparo
pwm3_config();
pwm4_config(); //DAC pwm
pwm5_config(); //Gera sinal CNVST para iniciar conversao do AD7634
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
pwm_mep_sfo_init();
}
void EPwmSetup()
{
// 使能前10个Epwm的I/O引脚
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
//InitEPwm6Gpio();
EPwm1Config(0, 0);
EPwm2Config(0, 0);
EPwm3Config(0, 0);
EPwm4Config(0, 0);
EPwm5Config(0, 0);
}
static void init_peripherals_drivers(void)
{
uint16_t i;
/// Initialization of HRADC boards
stop_DMA();
decimation_factor = (uint16_t) roundf(HRADC_FREQ_SAMP / ISR_CONTROL_FREQ);
decimation_coeff = 1.0 / (float) decimation_factor;
HRADCs_Info.enable_Sampling = 0;
HRADCs_Info.n_HRADC_boards = NUM_HRADC_BOARDS;
Init_DMA_McBSP_nBuffers(NUM_HRADC_BOARDS, decimation_factor, HRADC_SPI_CLK);
Init_SPIMaster_McBSP(HRADC_SPI_CLK);
Init_SPIMaster_Gpio();
InitMcbspa20bit();
DELAY_US(500000);
send_ipc_lowpriority_msg(0,Enable_HRADC_Boards);
DELAY_US(2000000);
for(i = 0; i < NUM_HRADC_BOARDS; i++)
{
Init_HRADC_Info(&HRADCs_Info.HRADC_boards[i], i, decimation_factor,
buffers_HRADC[i], TRANSDUCER_GAIN[i]);
Config_HRADC_board(&HRADCs_Info.HRADC_boards[i], TRANSDUCER_OUTPUT_TYPE[i],
HRADC_HEATER_ENABLE[i], HRADC_MONITOR_ENABLE[i]);
}
Config_HRADC_SoC(HRADC_FREQ_SAMP);
/**
*
* Initialization of PWM modules. PWM signals are mapped as the following:
*
* ePWM => Signal POF transmitter
* channel Name on BCB
*
* ePWM1A => Q1_MOD_1 PWM1
* ePWM1B => Q1_MOD_5 PWM2
* ePWM2A => Q2_MOD_1 PWM3
* ePWM2B => Q2_MOD_5 PWM4
* ePWM3A => Q1_MOD_2 PWM5
* ePWM3B => Q1_MOD_6 PWM6
* ePWM4A => Q2_MOD_2 PWM7
* ePWM4B => Q2_MOD_6 PWM8
* ePWM5A => Q1_MOD_3 PWM9
* ePWM5B => Q1_MOD_7 PWM10
* ePWM6A => Q2_MOD_3 PWM11
* ePWM6B => Q2_MOD_7 PWM12
* ePWM7A => Q1_MOD_4 PWM13
* ePWM7B => Q1_MOD_8 PWM14
* ePWM8A => Q2_MOD_4 PWM15
* ePWM8B => Q2_MOD_8 PWM16
*
*/
g_pwm_modules.num_modules = 8;
PWM_MODULATOR_Q1_MOD_1_5 = &EPwm1Regs;
PWM_MODULATOR_Q2_MOD_1_5 = &EPwm2Regs;
PWM_MODULATOR_Q1_MOD_2_6 = &EPwm3Regs;
PWM_MODULATOR_Q2_MOD_2_6 = &EPwm4Regs;
PWM_MODULATOR_Q1_MOD_3_7 = &EPwm5Regs;
PWM_MODULATOR_Q2_MOD_3_7 = &EPwm6Regs;
PWM_MODULATOR_Q1_MOD_4_8 = &EPwm7Regs;
PWM_MODULATOR_Q2_MOD_4_8 = &EPwm8Regs;
disable_pwm_outputs();
disable_pwm_tbclk();
init_pwm_mep_sfo();
init_pwm_module(PWM_MODULATOR_Q1_MOD_1_5, PWM_FREQ, 0, PWM_Sync_Master, 0,
PWM_ChB_Independent, PWM_DEAD_TIME);
init_pwm_module(PWM_MODULATOR_Q2_MOD_1_5, PWM_FREQ, 1, PWM_Sync_Slave, 180,
PWM_ChB_Independent, PWM_DEAD_TIME);
cfg_pwm_module_h_brigde_q2(PWM_MODULATOR_Q2_MOD_1_5);
init_pwm_module(PWM_MODULATOR_Q1_MOD_2_6, PWM_FREQ, 0, PWM_Sync_Slave, 45,
PWM_ChB_Independent, PWM_DEAD_TIME);
init_pwm_module(PWM_MODULATOR_Q2_MOD_2_6, PWM_FREQ, 3, PWM_Sync_Slave, 225,
PWM_ChB_Independent, PWM_DEAD_TIME);
cfg_pwm_module_h_brigde_q2(PWM_MODULATOR_Q2_MOD_2_6);
init_pwm_module(PWM_MODULATOR_Q1_MOD_3_7, PWM_FREQ, 0, PWM_Sync_Slave, 90,
PWM_ChB_Independent, PWM_DEAD_TIME);
init_pwm_module(PWM_MODULATOR_Q2_MOD_3_7, PWM_FREQ, 5, PWM_Sync_Slave, 270,
PWM_ChB_Independent, PWM_DEAD_TIME);
cfg_pwm_module_h_brigde_q2(PWM_MODULATOR_Q2_MOD_3_7);
init_pwm_module(PWM_MODULATOR_Q1_MOD_4_8, PWM_FREQ, 0, PWM_Sync_Slave, 135,
PWM_ChB_Independent, PWM_DEAD_TIME);
init_pwm_module(PWM_MODULATOR_Q2_MOD_4_8, PWM_FREQ, 7, PWM_Sync_Slave, 315,
PWM_ChB_Independent, PWM_DEAD_TIME);
cfg_pwm_module_h_brigde_q2(PWM_MODULATOR_Q2_MOD_4_8);
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
InitEPwm5Gpio();
InitEPwm6Gpio();
InitEPwm7Gpio();
InitEPwm8Gpio();
/// Initialization of timers
InitCpuTimers();
ConfigCpuTimer(&CpuTimer0, C28_FREQ_MHZ, 1000000);
CpuTimer0Regs.TCR.bit.TIE = 0;
}
