mali_error kbase_hw_set_issues_mask(kbase_device *kbdev)
{
const base_hw_issue *issues;
u32 gpu_id;
gpu_id = kbdev->gpu_props.props.raw_props.gpu_id;
switch (gpu_id) {
case GPU_ID_MAKE(GPU_ID_PI_T60X, 0, 0, GPU_ID_S_15DEV0):
issues = base_hw_issues_t60x_r0p0_15dev0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T60X, 0, 0, GPU_ID_S_EAC):
issues = base_hw_issues_t60x_r0p0_eac;
break;
case GPU_ID_MAKE(GPU_ID_PI_T60X, 0, 1, 0):
issues = base_hw_issues_t60x_r0p1;
break;
case GPU_ID_MAKE(GPU_ID_PI_T65X, 0, 1, 0):
issues = base_hw_issues_t65x_r0p1;
break;
case GPU_ID_MAKE(GPU_ID_PI_T62X, 0, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T62X, 0, 0, 1):
issues = base_hw_issues_t62x_r0p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T62X, 0, 1, 0):
issues = base_hw_issues_t62x_r0p1;
break;
case GPU_ID_MAKE(GPU_ID_PI_T62X, 1, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T62X, 1, 0, 1):
issues = base_hw_issues_t62x_r1p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T67X, 0, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T67X, 0, 0, 1):
issues = base_hw_issues_t67x_r0p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T67X, 0, 1, 0):
issues = base_hw_issues_t67x_r0p1;
break;
case GPU_ID_MAKE(GPU_ID_PI_T67X, 1, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T67X, 1, 0, 1):
issues = base_hw_issues_t67x_r1p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T75X, 0, 0, 0):
issues = base_hw_issues_t75x_r0p0;
break;
default:
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "Unknown GPU ID %x", gpu_id);
return MALI_ERROR_FUNCTION_FAILED;
}
KBASE_DEBUG_PRINT_INFO(KBASE_CORE, "GPU identified as 0x%04x r%dp%d status %d", (gpu_id & GPU_ID_VERSION_PRODUCT_ID) >> GPU_ID_VERSION_PRODUCT_ID_SHIFT, (gpu_id & GPU_ID_VERSION_MAJOR) >> GPU_ID_VERSION_MAJOR_SHIFT, (gpu_id & GPU_ID_VERSION_MINOR) >> GPU_ID_VERSION_MINOR_SHIFT, (gpu_id & GPU_ID_VERSION_STATUS) >> GPU_ID_VERSION_STATUS_SHIFT);
for (; *issues != BASE_HW_ISSUE_END; issues++)
set_bit(*issues, &kbdev->hw_issues_mask[0]);
return MALI_ERROR_NONE;
}
static int pm_callback_runtime_on(kbase_device *kbdev)
{
int ret;
struct clk *mout_vpll = NULL, *aclk_g3d_sw = NULL, *aclk_g3d_dout = NULL;
struct device *dev = kbdev->osdev.dev;
struct exynos_context * platform = (struct exynos_context *) kbdev->platform_context;
sec_debug_aux_log(SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE,
"g3d turn on++++");
kbase_platform_clock_on(kbdev);
#ifdef CONFIG_MALI_T6XX_DVFS
//if (kbase_platform_dvfs_enable(true, MALI_DVFS_START_FREQ) != MALI_TRUE)
// return -EPERM;
#endif
mout_vpll = clk_get(dev, "mout_vpll");
if (IS_ERR(mout_vpll)) {
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "failed to clk_get [mout_vpll]\n");
return 0;
}
aclk_g3d_dout = clk_get(dev, "aclk_g3d_dout");
if (IS_ERR(aclk_g3d_dout)) {
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "failed to clk_get [aclk_g3d_dout]\n");
return 0;
}
aclk_g3d_sw = clk_get(dev, "aclk_g3d_sw");
if (IS_ERR(aclk_g3d_sw)) {
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "failed to clk_get [aclk_g3d_sw]\n");
return 0;
}
ret = clk_set_parent(platform->aclk_g3d, aclk_g3d_sw);
if (ret < 0) {
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "failed to clk_set_parent [platform->aclk_g3d]\n");
return 0;
}
ret = clk_set_parent(aclk_g3d_sw, aclk_g3d_dout);
if (ret < 0) {
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "failed to clk_set_parent [aclk_g3d_sw]\n");
return 0;
}
ret = clk_set_parent(aclk_g3d_dout, mout_vpll);
if (ret < 0) {
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "failed to clk_set_parent [aclk_g3d_dout]\n");
return 0;
}
sec_debug_aux_log(SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE,
"g3d turn on---");
return 0;
}
uintptr_t kbasep_get_config_value(struct kbase_device *kbdev, const kbase_attribute *attributes, int attribute_id)
{
const kbase_attribute *attr;
KBASE_DEBUG_ASSERT(attributes != NULL);
attr = kbasep_get_next_attribute(attributes, attribute_id);
if (attr != NULL)
return attr->data;
/* default values */
switch (attribute_id) {
case KBASE_CONFIG_ATTR_GPU_IRQ_THROTTLE_TIME_US:
return DEFAULT_IRQ_THROTTLE_TIME_US;
/* Begin scheduling defaults */
case KBASE_CONFIG_ATTR_JS_SCHEDULING_TICK_NS:
return DEFAULT_JS_SCHEDULING_TICK_NS;
case KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS:
return DEFAULT_JS_SOFT_STOP_TICKS;
case KBASE_CONFIG_ATTR_JS_SOFT_STOP_TICKS_CL:
return DEFAULT_JS_SOFT_STOP_TICKS_CL;
case KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_SS:
if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_8408))
return DEFAULT_JS_HARD_STOP_TICKS_SS_HW_ISSUE_8408;
else
return DEFAULT_JS_HARD_STOP_TICKS_SS;
case KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_CL:
return DEFAULT_JS_HARD_STOP_TICKS_CL;
case KBASE_CONFIG_ATTR_JS_HARD_STOP_TICKS_NSS:
return DEFAULT_JS_HARD_STOP_TICKS_NSS;
case KBASE_CONFIG_ATTR_JS_CTX_TIMESLICE_NS:
return DEFAULT_JS_CTX_TIMESLICE_NS;
case KBASE_CONFIG_ATTR_JS_CFS_CTX_RUNTIME_INIT_SLICES:
return DEFAULT_JS_CFS_CTX_RUNTIME_INIT_SLICES;
case KBASE_CONFIG_ATTR_JS_CFS_CTX_RUNTIME_MIN_SLICES:
return DEFAULT_JS_CFS_CTX_RUNTIME_MIN_SLICES;
case KBASE_CONFIG_ATTR_JS_RESET_TICKS_SS:
if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_8408))
return DEFAULT_JS_RESET_TICKS_SS_HW_ISSUE_8408;
else
return DEFAULT_JS_RESET_TICKS_SS;
case KBASE_CONFIG_ATTR_JS_RESET_TICKS_CL:
return DEFAULT_JS_RESET_TICKS_CL;
case KBASE_CONFIG_ATTR_JS_RESET_TICKS_NSS:
return DEFAULT_JS_RESET_TICKS_NSS;
case KBASE_CONFIG_ATTR_JS_RESET_TIMEOUT_MS:
return DEFAULT_JS_RESET_TIMEOUT_MS;
/* End scheduling defaults */
case KBASE_CONFIG_ATTR_POWER_MANAGEMENT_CALLBACKS:
return 0;
case KBASE_CONFIG_ATTR_PLATFORM_FUNCS:
return 0;
case KBASE_CONFIG_ATTR_SECURE_BUT_LOSS_OF_PERFORMANCE:
return DEFAULT_SECURE_BUT_LOSS_OF_PERFORMANCE;
case KBASE_CONFIG_ATTR_CPU_SPEED_FUNC:
return DEFAULT_CPU_SPEED_FUNC;
case KBASE_CONFIG_ATTR_GPU_SPEED_FUNC:
return 0;
case KBASE_CONFIG_ATTR_ARID_LIMIT:
return DEFAULT_ARID_LIMIT;
case KBASE_CONFIG_ATTR_AWID_LIMIT:
return DEFAULT_AWID_LIMIT;
case KBASE_CONFIG_ATTR_ALTERNATIVE_HWC:
return DEFAULT_ALTERNATIVE_HWC;
case KBASE_CONFIG_ATTR_POWER_MANAGEMENT_DVFS_FREQ:
return DEFAULT_PM_DVFS_FREQ;
case KBASE_CONFIG_ATTR_PM_SHADER_POWEROFF_TIME:
return DEFAULT_PM_SHADER_POWEROFF_TIME;
default:
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "kbasep_get_config_value. Cannot get value of attribute with id=%d and no default value defined", attribute_id);
return 0;
}
}
mali_error kbase_hw_set_issues_mask(kbase_device *kbdev)
{
const base_hw_issue *issues;
u32 gpu_id;
u32 impl_tech;
gpu_id = kbdev->gpu_props.props.raw_props.gpu_id;
impl_tech = kbdev->gpu_props.props.thread_props.impl_tech;
if (impl_tech != IMPLEMENTATION_MODEL) {
switch (gpu_id) {
case GPU_ID_MAKE(GPU_ID_PI_T60X, 0, 0, GPU_ID_S_15DEV0):
issues = base_hw_issues_t60x_r0p0_15dev0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T60X, 0, 0, GPU_ID_S_EAC):
issues = base_hw_issues_t60x_r0p0_eac;
break;
case GPU_ID_MAKE(GPU_ID_PI_T60X, 0, 1, 0):
issues = base_hw_issues_t60x_r0p1;
break;
case GPU_ID_MAKE(GPU_ID_PI_T62X, 0, 1, 0):
issues = base_hw_issues_t62x_r0p1;
break;
case GPU_ID_MAKE(GPU_ID_PI_T62X, 1, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T62X, 1, 0, 1):
issues = base_hw_issues_t62x_r1p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T67X, 1, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T67X, 1, 0, 1):
issues = base_hw_issues_t67x_r1p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T76X, 0, 0, 0):
issues = base_hw_issues_t76x_r0p0_beta;
break;
case GPU_ID_MAKE(GPU_ID_PI_T76X, 0, 0, 1):
issues = base_hw_issues_t76x_r0p0;
break;
case GPU_ID_MAKE(GPU_ID_PI_T72X, 0, 0, 0):
case GPU_ID_MAKE(GPU_ID_PI_T72X, 0, 0, 1):
issues = base_hw_issues_t72x_r0p0;
break;
default:
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "Unknown GPU ID %x", gpu_id);
return MALI_ERROR_FUNCTION_FAILED;
}
} else {
/* Software model */
switch (gpu_id >> GPU_ID_VERSION_PRODUCT_ID_SHIFT) {
case GPU_ID_PI_T60X:
case GPU_ID_PI_T62X:
case GPU_ID_PI_T67X:
issues = base_hw_issues_model_t6xx;
break;
case GPU_ID_PI_T72X:
issues = base_hw_issues_model_t72x;
break;
case GPU_ID_PI_T76X:
issues = base_hw_issues_model_t7xx;
break;
default:
KBASE_DEBUG_PRINT_ERROR(KBASE_CORE, "Unknown GPU ID %x", gpu_id);
return MALI_ERROR_FUNCTION_FAILED;
}
}
KBASE_DEBUG_PRINT_INFO(KBASE_CORE, "GPU identified as 0x%04x r%dp%d status %d", (gpu_id & GPU_ID_VERSION_PRODUCT_ID) >> GPU_ID_VERSION_PRODUCT_ID_SHIFT, (gpu_id & GPU_ID_VERSION_MAJOR) >> GPU_ID_VERSION_MAJOR_SHIFT, (gpu_id & GPU_ID_VERSION_MINOR) >> GPU_ID_VERSION_MINOR_SHIFT, (gpu_id & GPU_ID_VERSION_STATUS) >> GPU_ID_VERSION_STATUS_SHIFT);
for (; *issues != BASE_HW_ISSUE_END; issues++)
set_bit(*issues, &kbdev->hw_issues_mask[0]);
return MALI_ERROR_NONE;
}