int adreno_ringbuffer_read_pfp_ucode(struct kgsl_device *device)
{
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
	int ret;

	if (adreno_dev->pfp_fw == NULL) {
		int len;
		void *ptr;

		ret = _load_firmware(device,
			adreno_dev->gpucore->pfpfw_name, &ptr, &len);
		if (ret)
			goto err;

		/* PFP size shold be dword aligned */
		if (len % sizeof(uint32_t) != 0) {
			KGSL_DRV_ERR(device, "Bad PFP microcode size: %d\n",
				len);
			kfree(ptr);
			ret = -ENOMEM;
			goto err;
		}

		adreno_dev->pfp_fw_size = len / sizeof(uint32_t);
		adreno_dev->pfp_fw = ptr;
		adreno_dev->pfp_fw_version = adreno_dev->pfp_fw[5];
	}

	return 0;

err:
	KGSL_DRV_CRIT(device, "Failed to read pfp microcode %s\n",
		adreno_dev->gpucore->pfpfw_name);
	return ret;
}
static void a2xx_rbbm_intrcallback(struct kgsl_device *device)
{
	unsigned int status = 0;
	unsigned int rderr = 0;
	unsigned int addr = 0;
	const char *source;

	adreno_regread(device, REG_RBBM_INT_STATUS, &status);

	if (status & RBBM_INT_CNTL__RDERR_INT_MASK) {
		adreno_regread(device, REG_RBBM_READ_ERROR, &rderr);
		source = (rderr & RBBM_READ_ERROR_REQUESTER)
			 ? "host" : "cp";
		
		addr = (rderr & RBBM_READ_ERROR_ADDRESS_MASK) >> 2;

		if (addr == REG_CP_INT_STATUS &&
			rderr & RBBM_READ_ERROR_ERROR &&
			rderr & RBBM_READ_ERROR_REQUESTER)
			KGSL_DRV_WARN(device,
				"rbbm read error interrupt: %s reg: %04X\n",
				source, addr);
		else
			KGSL_DRV_CRIT(device,
				"rbbm read error interrupt: %s reg: %04X\n",
				source, addr);
	}
int adreno_ringbuffer_read_pm4_ucode(struct kgsl_device *device)
{
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
	int ret;

	if (adreno_dev->pm4_fw == NULL) {
		int len;
		void *ptr;

		ret = _load_firmware(device,
			adreno_dev->gpucore->pm4fw_name, &ptr, &len);

		if (ret)
			goto err;

		/* PM4 size is 3 dword aligned plus 1 dword of version */
		if (len % ((sizeof(uint32_t) * 3)) != sizeof(uint32_t)) {
			KGSL_DRV_ERR(device, "Bad pm4 microcode size: %d\n",
				len);
			kfree(ptr);
			ret = -ENOMEM;
			goto err;
		}

		adreno_dev->pm4_fw_size = len / sizeof(uint32_t);
		adreno_dev->pm4_fw = ptr;
		adreno_dev->pm4_fw_version = adreno_dev->pm4_fw[1];
	}

	return 0;

err:
#ifdef CONFIG_MACH_LGE
	if (system_state != SYSTEM_RESTART)
#endif
	KGSL_DRV_CRIT(device, "Failed to read pm4 microcode %s\n",
		adreno_dev->gpucore->pm4fw_name);
	return ret;
}
Exemple #4
0
static void a2xx_rbbm_intrcallback(struct kgsl_device *device)
{
	unsigned int status = 0;
	unsigned int rderr = 0;

	adreno_regread(device, REG_RBBM_INT_STATUS, &status);

	if (status & RBBM_INT_CNTL__RDERR_INT_MASK) {
		union rbbm_read_error_u rerr;
		adreno_regread(device, REG_RBBM_READ_ERROR, &rderr);
		rerr.val = rderr;
		if (rerr.f.read_address == REG_CP_INT_STATUS &&
			rerr.f.read_error &&
			rerr.f.read_requester)
			KGSL_DRV_WARN(device,
				"rbbm read error interrupt: %08x\n", rderr);
		else
			KGSL_DRV_CRIT(device,
				"rbbm read error interrupt: %08x\n", rderr);
	}

	status &= RBBM_INT_MASK;
	adreno_regwrite(device, REG_RBBM_INT_ACK, status);
}