void kinetis_pinirqdisable(uint32_t pinset) { #ifdef HAVE_PORTINTS uintptr_t base; uint32_t regval; unsigned int port; unsigned int pin; /* Get the port number and pin number */ port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; pin = (pinset & _PIN_MASK) >> _PIN_SHIFT; DEBUGASSERT(port < KINETIS_NPORTS); if (port < KINETIS_NPORTS) { /* Get the base address of PORT block for this port */ base = KINETIS_PORT_BASE(port); /* Clear the IRQC field of the port PCR register in order to disable * the interrupt. */ regval = getreg32(base + KINETIS_PORT_PCR_OFFSET(pin)); regval &= ~PORT_PCR_IRQC_MASK; putreg32(regval, base + KINETIS_PORT_PCR_OFFSET(pin)); } #endif /* HAVE_PORTINTS */ }
void kinetis_pinirqenable(uint32_t pinset) { #ifdef HAVE_PORTINTS uintptr_t base; uint32_t regval; unsigned int port; unsigned int pin; /* Get the port number and pin number */ port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; pin = (pinset & _PIN_MASK) >> _PIN_SHIFT; DEBUGASSERT(port < KINETIS_NPORTS); if (port < KINETIS_NPORTS) { /* Get the base address of PORT block for this port */ base = KINETIS_PORT_BASE(port); /* Modify the IRQC field of the port PCR register in order to enable * the interrupt. */ regval = getreg32(base + KINETIS_PORT_PCR_OFFSET(pin)); regval &= ~PORT_PCR_IRQC_MASK; switch (pinset & _PIN_INT_MASK) { case PIN_INT_ZERO : /* Interrupt when logic zero */ regval |= PORT_PCR_IRQC_ZERO; break; case PIN_INT_RISING : /* Interrupt on rising edge*/ regval |= PORT_PCR_IRQC_RISING; break; case PIN_INT_BOTH : /* Interrupt on falling edge */ regval |= PORT_PCR_IRQC_FALLING; break; case PIN_DMA_FALLING : /* nterrupt on either edge */ regval |= PORT_PCR_IRQC_BOTH; break; case PIN_INT_ONE : /* IInterrupt when logic one */ regval |= PORT_PCR_IRQC_ONE; break; default: return; } putreg32(regval, base + KINETIS_PORT_PCR_OFFSET(pin)); } #endif /* HAVE_PORTINTS */ }
void kinetis_pindmaenable(uint32_t pinset) { uintptr_t base; uint32_t regval; unsigned int port; unsigned int pin; /* Get the port number and pin number */ port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; pin = (pinset & _PIN_MASK) >> _PIN_SHIFT; DEBUGASSERT(port < KINETIS_NPORTS); if (port < KINETIS_NPORTS) { /* Get the base address of PORT block for this port */ base = KINETIS_PORT_BASE(port); /* Modify the IRQC field of the port PCR register in order to enable DMA. */ regval = getreg32(base + KINETIS_PORT_PCR_OFFSET(pin)); regval &= ~PORT_PCR_IRQC_MASK; switch (pinset & _PIN_INT_MASK) { case PIN_DMA_RISING : /* DMA Request on rising edge */ regval |= PORT_PCR_IRQC_DMARISING; break; case PIN_DMA_FALLING : /* DMA Request on falling edge */ regval |= PORT_PCR_IRQC_DMAFALLING; break; case PIN_DMA_BOTH : /* DMA Request on either edge */ regval |= PORT_PCR_IRQC_DMABOTH; break; default: return; } putreg32(regval, base + KINETIS_PORT_PCR_OFFSET(pin)); } }
void kinetis_pindmadisable(uint32_t pinset) { uintptr_t base; uint32_t regval; unsigned int port; unsigned int pin; /* Get the port number and pin number */ port = (pinset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; pin = (pinset & _PIN_MASK) >> _PIN_SHIFT; DEBUGASSERT(port < KINETIS_NPORTS); if (port < KINETIS_NPORTS) { /* Clear the IRQC field of the port PCR register in order to disable DMA. */ regval = getreg32(base + KINETIS_PORT_PCR_OFFSET(pin)); regval &= ~PORT_PCR_IRQC_MASK; putreg32(regval, base + KINETIS_PORT_PCR_OFFSET(pin)); } }
int kinetis_pinconfig(uint32_t cfgset) { uintptr_t base; uint32_t regval; unsigned int port; unsigned int pin; unsigned int mode; /* Get the port number and pin number */ port = (cfgset & _PIN_PORT_MASK) >> _PIN_PORT_SHIFT; pin = (cfgset & _PIN_MASK) >> _PIN_SHIFT; DEBUGASSERT(port < KINETIS_NPORTS); if (port < KINETIS_NPORTS) { /* Get the base address of PORT block for this port */ base = KINETIS_PORT_BASE(port); /* Get the port mode */ mode = (cfgset & _PIN_MODE_MASK) >> _PIN_MODE_SHIFT; /* Special case analog port mode. In this case, not of the digital * options are applicable. */ if (mode == _PIN_MODE_ANALOG) { /* Set the analog mode with all digital options zeroed */ regval = PORT_PCR_MUX_ANALOG | PORT_PCR_IRQC_DISABLED; putreg32(regval, base + KINETIS_PORT_PCR_OFFSET(pin)); } else { /* Configure the digital pin options */ regval = (mode << PORT_PCR_MUX_SHIFT); if ((cfgset & _PIN_IO_MASK) == _PIN_INPUT) { /* Handle input-only digital options */ /* Check for pull-up or pull-down */ if ((cfgset & _PIN_INPUT_PULLMASK) == _PIN_INPUT_PULLDOWN) { regval |= PORT_PCR_PE; } else if ((cfgset & _PIN_INPUT_PULLMASK) == _PIN_INPUT_PULLUP) { regval |= (PORT_PCR_PE | PORT_PCR_PS); } } else { /* Handle output-only digital options */ /* Check for slow slew rate setting */ if ((cfgset & _PIN_OUTPUT_SLEW_MASK) == _PIN_OUTPUT_SLOW) { regval |= PORT_PCR_SRE; } /* Check for open drain output */ if ((cfgset & _PIN_OUTPUT_OD_MASK) == _PIN_OUTPUT_OPENDRAIN) { regval |= PORT_PCR_ODE; } /* Check for high drive output */ if ((cfgset & _PIN_OUTPUT_DRIVE_MASK) == _PIN_OUTPUT_HIGHDRIVE) { regval |= PORT_PCR_DSE; } } /* Check for passive filter enable. Passive Filter configuration * is valid in all digital pin muxing modes. */ if ((cfgset & PIN_PASV_FILTER) != 0) { regval |= PORT_PCR_PFE; } /* Set the digital mode with all of the selected options */ putreg32(regval, base + KINETIS_PORT_PCR_OFFSET(pin)); /* Check for digital filter enable. Digital Filter configuration * is valid in all digital pin muxing modes. */ regval = getreg32(base + KINETIS_PORT_DFER_OFFSET); if ((cfgset & PIN_DIG_FILTER) != 0) { regval |= (1 << pin); } else { regval &= ~(1 << pin); } putreg32(regval, base + KINETIS_PORT_DFER_OFFSET); /* Additional configuration for the case of Alternative 1 (GPIO) modes */ if (mode == _PIN_MODE_GPIO) { /* Set the GPIO port direction */ base = KINETIS_GPIO_BASE(port); regval = getreg32(base + KINETIS_GPIO_PDDR_OFFSET); if ((cfgset & _PIN_IO_MASK) == _PIN_INPUT) { /* Select GPIO input */ regval &= ~(1 << pin); putreg32(regval, base + KINETIS_GPIO_PDDR_OFFSET); } else /* if ((cfgset & _PIN_IO_MASK) == _PIN_OUTPUT) */ { /* Select GPIO input */ regval |= (1 << pin); putreg32(regval, base + KINETIS_GPIO_PDDR_OFFSET); /* Set the initial value of the GPIO output */ kinetis_gpiowrite(cfgset, ((cfgset & GPIO_OUTPUT_ONE) != 0)); } } } return OK; }