void __init plat_mem_setup(void)
{
unsigned long fdt_start;
set_io_port_base(KSEG1);
/* Get the position of the FDT passed by the bootloader */
fdt_start = fw_getenvl("fdt_start");
if (fdt_start)
__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
else if (fw_passed_dtb)
__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
if (mips_machtype != ATH79_MACH_GENERIC_OF) {
ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE);
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE);
ath79_detect_sys_type();
ath79_ddr_ctrl_init();
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
/* OF machines should use the reset driver */
_machine_restart = ath79_restart;
}
_machine_halt = ath79_halt;
pm_power_off = ath79_halt;
}
void __init prom_setup_cmdline(void)
{
char *cp;
int prom_argc;
char **prom_argv;
int i;
prom_argc = fw_arg0;
prom_argv = (char **)KSEG0ADDR(fw_arg1);
cp = &(arcs_cmdline[0]);
for (i = 1; i < prom_argc; i++) {
prom_argv[i] = (char *)KSEG0ADDR(prom_argv[i]);
/* default bootargs has "console=/dev/ttyS0" yet console won't
* show up at all if you include the '/dev/' nowadays ... */
if (match_tag(prom_argv[i], "console=/dev/")) {
char *ptr = prom_argv[i] + strlen("console=/dev/");
strcpy(cp, "console=");
cp += strlen("console=");
strcpy(cp, ptr);
cp += strlen(ptr);
*cp++ = ' ';
continue;
}
strcpy(cp, prom_argv[i]);
cp += strlen(prom_argv[i]);
*cp++ = ' ';
}
if (prom_argc > 1)
--cp; /* trailing space */
*cp = '\0';
}
/**
* frees the "xhci_container_ctx" pointer passed
*
* @param ptr pointer to "xhci_container_ctx" to be freed
* @return none
*/
static void xhci_free_container_ctx(struct xhci_container_ctx *ctx)
{
if (ctx) {
if (ctx->bytes) {
free(KSEG0ADDR(ctx->bytes));
}
free(KSEG0ADDR(ctx));
}
}
/**
* frees the "segment" pointer passed
*
* @param ptr pointer to "segement" to be freed
* @return none
*/
static void xhci_segment_free(struct xhci_segment *seg)
{
if (seg) {
if (seg->trbs) {
free(KSEG0ADDR(seg->trbs));
seg->trbs = NULL;
}
free(KSEG0ADDR(seg));
}
}
int sgiwd93_release(struct Scsi_Host *instance)
{
free_irq(SGI_WD93_0_IRQ, sgiwd93_intr);
free_page(KSEG0ADDR(hdata->dma_bounce_buffer));
wd33c93_release();
if(!sgi_guiness) {
free_irq(SGI_WD93_1_IRQ, sgiwd93_intr);
free_page(KSEG0ADDR(hdata1->dma_bounce_buffer));
wd33c93_release();
}
return 1;
}
/**
* frees all the memory allocated
*
* @param ptr pointer to "xhci_ctrl" to be cleaned up
* @return none
*/
void xhci_cleanup(struct xhci_ctrl *ctrl)
{
if (ctrl->event_ring)
xhci_ring_free(ctrl->event_ring);
if (ctrl->cmd_ring)
xhci_ring_free(ctrl->cmd_ring);
if (ctrl)
xhci_free_virt_devices(ctrl);
if (ctrl->erst.entries)
free(KSEG0ADDR(ctrl->erst.entries));
if (ctrl->dcbaa)
free(KSEG0ADDR(ctrl->dcbaa));
memset(ctrl, '\0', sizeof(struct xhci_ctrl));
}
static int rc32434_remove(struct platform_device *pdev)
{
struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data;
if (bif->dev != NULL) {
struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
if (lp != NULL) {
if (lp->eth_regs)
iounmap((void*)lp->eth_regs);
if (lp->rx_dma_regs)
iounmap((void*)lp->rx_dma_regs);
if (lp->tx_dma_regs)
iounmap((void*)lp->tx_dma_regs);
if (lp->td_ring)
kfree((void*)KSEG0ADDR(lp->td_ring));
#ifdef RC32434_PROC_DEBUG
if (lp->ps) {
remove_proc_entry(bif->name, proc_net);
}
#endif
kfree(lp);
}
platform_set_drvdata(pdev, NULL);
unregister_netdev(bif->dev);
free_netdev(bif->dev);
kfree(bif->dev);
}
return 0;
}
/**
* frees the virtual devices for "xhci_ctrl" pointer passed
*
* @param ptr pointer to "xhci_ctrl" whose virtual devices are to be freed
* @return none
*/
static void xhci_free_virt_devices(struct xhci_ctrl *ctrl)
{
int i;
int slot_id;
struct xhci_virt_device *virt_dev;
/*
* refactored here to loop through all virt_dev
* Slot ID 0 is reserved
*/
for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) {
virt_dev = ctrl->devs[slot_id];
if (!virt_dev)
continue;
ctrl->dcbaa->dev_context_ptrs[slot_id] = 0;
for (i = 0; i < 31; ++i) {
if (virt_dev->eps[i].ring)
xhci_ring_free(virt_dev->eps[i].ring);
}
if (virt_dev->in_ctx)
xhci_free_container_ctx(virt_dev->in_ctx);
if (virt_dev->out_ctx)
xhci_free_container_ctx(virt_dev->out_ctx);
free(KSEG0ADDR(virt_dev));
/* make sure we are pointing to NULL */
ctrl->devs[slot_id] = NULL;
}
}
/*
* Use the REX prom calls to get hold of the memory bitmap, and thence
* determine memory size.
*/
static inline void rex_setup_memory_region(void)
{
int i, bitmap_size;
unsigned long mem_start = 0, mem_size = 0;
memmap *bm;
/* some free 64k */
bm = (memmap *)KSEG0ADDR(0x28000);
bitmap_size = rex_getbitmap(bm);
for (i = 0; i < bitmap_size; i++) {
/* FIXME: very simplistically only add full sets of pages */
if (bm->bitmap[i] == 0xff)
mem_size += (8 * bm->pagesize);
else if (!mem_size)
mem_start += (8 * bm->pagesize);
else {
add_memory_region(mem_start, mem_size, BOOT_MEM_RAM);
mem_start += mem_size + (8 * bm->pagesize);
mem_size = 0;
}
}
if (mem_size)
add_memory_region(mem_start, mem_size, BOOT_MEM_RAM);
}
void __init plat_mem_setup(void)
{
unsigned long fdt_start;
set_io_port_base(KSEG1);
/* Get the position of the FDT passed by the bootloader */
fdt_start = fw_getenvl("fdt_start");
if (fdt_start)
__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
#ifdef CONFIG_BUILTIN_DTB
else
__dt_setup_arch(__dtb_start);
#endif
ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE);
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE);
ath79_detect_sys_type();
ath79_ddr_ctrl_init();
if (mips_machtype != ATH79_MACH_GENERIC_OF)
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
_machine_restart = ath79_restart;
_machine_halt = ath79_halt;
pm_power_off = ath79_halt;
}
static void acacia_cleanup_module(void)
{
int i;
for (i = 0; acacia_iflist[i].iobase; i++) {
struct acacia_if_t * bif = &acacia_iflist[i];
if (bif->dev != NULL) {
struct acacia_local *lp =
(struct acacia_local *)bif->dev->priv;
if (lp != NULL) {
if (lp->eth_regs)
iounmap(lp->eth_regs);
if (lp->rx_dma_regs)
iounmap(lp->rx_dma_regs);
if (lp->tx_dma_regs)
iounmap(lp->tx_dma_regs);
if (lp->td_ring)
kfree((void*)KSEG0ADDR(lp->td_ring));
if (lp->rba)
kfree(lp->rba);
#ifdef ACACIA_PROC_DEBUG
if (lp->ps)
remove_proc_entry("net/rc32355",
NULL);
#endif
kfree(lp);
}
unregister_netdev(bif->dev);
kfree(bif->dev);
release_region(bif->iobase, 0x24C);
}
}
}
static void ar2313_free_descriptors(struct net_device *dev)
{
struct ar2313_private *sp = dev->priv;
if (sp->rx_ring != NULL) {
kfree((void *) KSEG0ADDR(sp->rx_ring));
sp->rx_ring = NULL;
sp->tx_ring = NULL;
}
}
void *
osl_cached(void *va)
{
#ifdef mips
return ((void*)KSEG0ADDR(va));
#else
return ((void*)va);
#endif /* mips */
}
void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
unsigned long addr = (unsigned long) vaddr;
#ifdef CONFIG_NONCOHERENT_IO
addr = KSEG0ADDR(addr);
#endif
free_pages(addr, get_order(size));
}
static inline void *to_ram_addr(void *addr)
{
u32 base;
base = KSEG0ADDR(RALINK_SOC_SDRAM_BASE);
if (((u32) addr > base) &&
((u32) addr < (base + RALINK_SOC_MEM_SIZE_MAX)))
return addr;
base = KSEG1ADDR(RALINK_SOC_SDRAM_BASE);
if (((u32) addr > base) &&
((u32) addr < (base + RALINK_SOC_MEM_SIZE_MAX)))
return addr;
/* some U-Boot variants uses physical addresses */
base = RALINK_SOC_SDRAM_BASE;
if (((u32) addr > base) &&
((u32) addr < (base + RALINK_SOC_MEM_SIZE_MAX)))
return (void *)KSEG0ADDR(addr);
return NULL;
}
static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
struct bcma_sflash *sflash = mtd->priv;
/* Check address range */
if ((from + len) > mtd->size)
return -EINVAL;
memcpy_fromio(buf, (void __iomem *)KSEG0ADDR(sflash->window + from),
len);
return len;
}
/*
DMA memory allocation, derived from pci_alloc_consistent.
However, the Au1000 data cache is coherent (when programmed
so), therefore we return KSEG0 address, not KSEG1.
*/
static void *dma_alloc(size_t size, dma_addr_t * dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC | GFP_DMA;
ret = (void *) __get_free_pages(gfp, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
*dma_handle = virt_to_bus(ret);
ret = (void *)KSEG0ADDR(ret);
}
return ret;
}
/**
* frees the "ring" pointer passed
*
* @param ptr pointer to "ring" to be freed
* @return none
*/
static void xhci_ring_free(struct xhci_ring *ring)
{
struct xhci_segment *seg;
struct xhci_segment *first_seg;
BUG_ON(!ring);
first_seg = ring->first_seg;
seg = first_seg->next;
while (seg != first_seg) {
struct xhci_segment *next = seg->next;
xhci_segment_free(seg);
seg = next;
}
xhci_segment_free(first_seg);
free(KSEG0ADDR(ring));
}
/*!
\brief This function is called to free allocated buffer.
\param vaddr the uncached pointer of the buffer
*/
void ifxusb_free_buf(void *vaddr)
{
uint32_t totalsize,page;
uint32_t *cached,*uncached;
if(vaddr != NULL)
{
uncached=vaddr;
uncached-=3;
totalsize=*(uncached+0);
page=*(uncached+1);
cached=(uint32_t *)(*(uncached+2));
if(totalsize && page==get_order(totalsize) && cached==(uint32_t *)(KSEG0ADDR(uncached)))
{
free_pages((unsigned long)cached, page);
return;
}
// the memory is not allocated by ifxusb_alloc_buf. Allowed but must be careful.
return;
}
}
struct prom_pmemblock * __init prom_getmdesc(void)
{
char *memsize_str;
unsigned int memsize;
memsize_str = prom_getenv("memsize");
if (!memsize_str) {
#ifdef CONFIG_MIPS_AVALANCHE_SOC
prom_printf("memsize not set in boot prom, set to default (64Mb)\n");
memsize = 0x04000000;
#else
prom_printf("memsize not set in boot prom, set to default (32Mb)\n");
memsize = 0x02000000;
#endif
} else {
#ifdef DEBUG
prom_printf("prom_memsize = %s\n", memsize_str);
#endif
memsize = simple_strtol(memsize_str, NULL, 0);
}
memset(mdesc, 0, sizeof(mdesc));
#if defined(CONFIG_MIPS_AVALANCHE_SOC)
#define PREV_MDESC(x) ((x) - 1)
{
struct prom_pmemblock *p_mdesc = &mdesc[0];
p_mdesc->type = yamon_dontuse;
p_mdesc->base = 0x00000000;
p_mdesc->size = AVALANCHE_SDRAM_BASE;
p_mdesc++;
p_mdesc->type = yamon_prom;
p_mdesc->base = PREV_MDESC(p_mdesc)->base + PREV_MDESC(p_mdesc)->size;
p_mdesc->size = PAGE_SIZE;
p_mdesc++;
p_mdesc->type = yamon_prom;
p_mdesc->base = PREV_MDESC(p_mdesc)->base + PREV_MDESC(p_mdesc)->size;
p_mdesc->size = (CONFIG_MIPS_AVALANCHE_LOAD_ADDRESS - KSEG0ADDR(AVALANCHE_SDRAM_BASE)) - PAGE_SIZE;
p_mdesc++;
p_mdesc->type = yamon_dontuse;
p_mdesc->base = PREV_MDESC(p_mdesc)->base + PREV_MDESC(p_mdesc)->size;
p_mdesc->size = CPHYSADDR(PFN_ALIGN(&_end)) - p_mdesc->base;
p_mdesc++;
p_mdesc->type = yamon_free;
p_mdesc->base = PREV_MDESC(p_mdesc)->base + PREV_MDESC(p_mdesc)->size;
p_mdesc->size = memsize - (CPHYSADDR(PFN_ALIGN(&_end)) - AVALANCHE_SDRAM_BASE);
}
#else
mdesc[0].type = yamon_dontuse;
mdesc[0].base = 0x00000000;
mdesc[0].size = 0x00001000;
mdesc[1].type = yamon_prom;
mdesc[1].base = 0x00001000;
mdesc[1].size = 0x000ef000;
#ifdef CONFIG_MIPS_MALTA
/*
* The area 0x000f0000-0x000fffff is allocated for BIOS memory by the
* south bridge and PCI access always forwarded to the ISA Bus and
* BIOSCS# is always generated.
* This mean that this area can't be used as DMA memory for PCI
* devices.
*/
mdesc[2].type = yamon_dontuse;
mdesc[2].base = 0x000f0000;
mdesc[2].size = 0x00010000;
#else
mdesc[2].type = yamon_prom;
mdesc[2].base = 0x000f0000;
mdesc[2].size = 0x00010000;
#endif
mdesc[3].type = yamon_dontuse;
mdesc[3].base = 0x00100000;
mdesc[3].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[3].base;
mdesc[4].type = yamon_free;
mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end));
mdesc[4].size = memsize - mdesc[4].base;
#endif /* CONFIG_MIPS_AVALANCHE_SOC */
return &mdesc[0];
}
static void dma_free(void *vaddr, size_t size)
{
vaddr = (void *)KSEG0ADDR(vaddr);
free_pages((unsigned long) vaddr, get_order(size));
}
ulong* get_reserved_buffer(void) {return KSEG0ADDR(buffer_ptr);}
void __init
prom_init(void)
{
unsigned long extmem = 0, off, data;
static unsigned long mem;
unsigned long off1, data1;
struct nvram_header *header;
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
/* These are not really being used anywhere - LR */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM947XX;
#endif
off = (unsigned long)prom_init;
data = *(unsigned long *)prom_init;
off1 = off + 4;
data1 = *(unsigned long *)off1;
/* Figure out memory size by finding aliases */
for (mem = (1 MB); mem < (128 MB); mem <<= 1) {
if ((*(unsigned long *)(off + mem) == data) &&
(*(unsigned long *)(off1 + mem) == data1))
break;
}
detectmem = mem;
#if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC)
if (mem == 128 MB) {
early_tlb_init();
/* Add one temporary TLB entries to map SDRAM Region 2.
* Physical Virtual
* 0x80000000 0xc0000000 (1st: 256MB)
* 0x90000000 0xd0000000 (2nd: 256MB)
*/
add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2),
ENTRYLO(SI_SDRAM_R2 + (256 MB)),
EXTVBASE, PM_256M);
off = EXTVBASE + __pa(off);
for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) {
if (*(unsigned long *)(off + extmem) == data)
break;
}
extmem -= mem;
/* Keep tlb entries back in consistent state */
early_tlb_init();
}
#endif /* CONFIG_HIGHMEM */
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
mem -= 0x1000;
/* CFE could have loaded nvram during netboot
* to top 32KB of RAM, Just check for nvram signature
* and copy it to nvram space embedded in linux
* image for later use by nvram driver.
*/
header = (struct nvram_header *)(KSEG0ADDR(mem - NVRAM_SPACE));
if (ltoh32(header->magic) == NVRAM_MAGIC) {
uint32 *src = (uint32 *)header;
uint32 *dst = (uint32 *)ram_nvram_buf;
uint32 i;
printk("Copying NVRAM bytes: %d from: 0x%p To: 0x%p\n", ltoh32(header->len),
src, dst);
for (i = 0; i < ltoh32(header->len) && i < NVRAM_SPACE; i += 4)
*dst++ = ltoh32(*src++);
}
add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM);
#if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC)
if (extmem) {
/* We should deduct 0x1000 from the second memory
* region, because of the fact that processor does prefetch.
* Now that we are deducting a page from second memory
* region, we could add the earlier deducted 4KB (from first bank)
* to the second region (the fact that 0x80000000 -> 0x88000000
* shadows 0x0 -> 0x8000000)
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
extmem -= 0x1000;
add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM);
}
#endif /* CONFIG_HIGHMEM */
}
static inline unsigned long kseg1_to_phys(volatile void * kseg1_addr)
{
return virt_to_phys((void*)KSEG0ADDR(kseg1_addr));
}