static void TPM_SetMode(uint32_t instance, uint8_t chl, TPM_Mode_Type mode)
{
TPM_InstanceTable[instance]->SC &= ~TPM_SC_CMOD_MASK;
TPM_InstanceTable[instance]->SC |= TPM_SC_CMOD(0);
switch(mode)
{
/* FSL: CnSC must be written all bit at one time */
case kTPM_Mode_EdgeAligned:
TPM_InstanceTable[instance]->SC &= ~TPM_SC_CPWMS_MASK;
TPM_InstanceTable[instance]->CONTROLS[chl].CnSC |= TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
TPM_InstanceTable[instance]->CONTROLS[chl].CnSC &= ~TPM_CnSC_MSA_MASK;
LIB_TRACE("chl:%d\r\n", chl);
LIB_TRACE("Cnsc:0x%X\r\n", TPM_InstanceTable[instance]->CONTROLS[chl].CnSC);
break;
case kTPM_Mode_CenterAligned:
TPM_InstanceTable[instance]->SC |= TPM_SC_CPWMS_MASK;
TPM_InstanceTable[instance]->CONTROLS[chl].CnSC |= TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
TPM_InstanceTable[instance]->CONTROLS[chl].CnSC &= ~TPM_CnSC_MSA_MASK;
case kFTM_Mode_InputCapture:
TPM_InstanceTable[instance]->SC &= ~TPM_SC_CPWMS_MASK;
TPM_InstanceTable[instance]->CONTROLS[chl].CnSC &= ~TPM_CnSC_MSB_MASK;
TPM_InstanceTable[instance]->CONTROLS[chl].CnSC &= ~TPM_CnSC_MSA_MASK;
break;
default:
break;
}
TPM_InstanceTable[instance]->SC &= ~TPM_SC_CMOD_MASK;
TPM_InstanceTable[instance]->SC |= TPM_SC_CMOD(1);
}
/**
* @brief 设置PDB转换频率
* @retval None
*/
static void _PDB_SetCounterPeriod(uint32_t srcClock, uint32_t timeInUs)
{
static const uint8_t MULT[4] = {1, 10, 20, 40};
uint32_t clkDiv,mult;
uint32_t i,j;
for(i=0;i<8;i++)
{
for(j=0;j<4;j++)
{
if((srcClock/1000000)*timeInUs/((1<<i)*MULT[j]) < 0xFFFF)
{
clkDiv = i;
mult = j;
break;
}
}
}
LIB_TRACE("clkDiv:%d Mult:%d\r\n",clkDiv, mult);
/* clk div */
PDB0->SC &= ~PDB_SC_PRESCALER_MASK;
PDB0->SC |= PDB_SC_PRESCALER(clkDiv);
/* muti */
PDB0->SC &= ~PDB_SC_MULT_MASK;
PDB0->SC |= PDB_SC_MULT(mult);
LIB_TRACE("MOD:%d\r\n", (srcClock/1000000)*timeInUs/((1<<clkDiv)*MULT[mult]));
PDB0->MOD = (srcClock/1000000)*timeInUs/((1<<clkDiv)*MULT[mult]);
PDB0->IDLY = (srcClock/1000000)*timeInUs/((1<<clkDiv)*MULT[mult]);
}
uint8_t FLASH_WriteSector(uint32_t addr, const uint8_t *buf, uint32_t len)
{
uint16_t step, ret, i;
union
{
uint32_t word;
uint8_t byte[4];
} dest;
dest.word = (uint32_t)addr;
FTF->FCCOB0 = PROGRAM_CMD;
switch(PROGRAM_CMD)
{
case PGM4:
step = 4;
break;
case PGM8:
step = 8;
break;
default:
LIB_TRACE("FLASH: no program cmd found!\r\n");
step = 4;
break;
}
for(i=0; i<len; i+=step)
{
/* set address */
FTF->FCCOB1 = dest.byte[2];
FTF->FCCOB2 = dest.byte[1];
FTF->FCCOB3 = dest.byte[0];
FTF->FCCOB4 = buf[3];
FTF->FCCOB5 = buf[2];
FTF->FCCOB6 = buf[1];
FTF->FCCOB7 = buf[0];
if(step == 8)
{
FTF->FCCOB8 = buf[7];
FTF->FCCOB9 = buf[6];
FTF->FCCOBA = buf[5];
FTF->FCCOBB = buf[4];
}
dest.word += step; buf += step;
__disable_irq();
ret = _cmd_lunch();
__enable_irq();
if(FLASH_OK != ret)
{
return FLASH_ERROR;
}
}
return FLASH_OK;
}
uint8_t I2C_Init(uint32_t MAP, uint32_t baudrate)
{
uint8_t i;
map_t * pq = (map_t*)&(MAP);
/* open drain and pull up */
for(i = 0; i < pq->pin_count; i++)
{
GPIO_Init(pq->io, pq->pin_start + i, kGPIO_Mode_OPP);
GPIO_Init(pq->io, pq->pin_start + i, kGPIO_Mode_OPP);
GPIO_PinWrite(pq->io, pq->pin_start + i, 1);
SetPinPull(pq->io, pq->pin_start + i, 1);
}
/* i2c_gpio struct setup */
i2c.instace = pq->io;
switch(MAP)
{
case I2C1_SCL_PE01_SDA_PE00:
i2c.scl = 1;i2c.sda = 0;
break;
case I2C0_SCL_PE19_SDA_PE18:
i2c.scl = 19;i2c.sda = 18;
break;
case I2C0_SCL_PF22_SDA_PF23:
i2c.scl = 22;i2c.sda = 23;
break;
case I2C0_SCL_PB00_SDA_PB01:
i2c.scl = 0;i2c.sda = 1;
break;
case I2C0_SCL_PB02_SDA_PB03:
i2c.scl = 2;i2c.sda = 3;
break;
case I2C1_SCL_PC10_SDA_PC11:
i2c.scl = 10;i2c.sda = 11;
break;
case I2C0_SCL_PD08_SDA_PD09:
i2c.scl = 8;i2c.sda = 9;
break;
case I2C0_SCL_PE24_SDA_PE25:
i2c.scl = 24;i2c.sda = 25;
break;
case I2C1_SCL_PC01_SDA_PC02:
i2c.scl = 1;i2c.sda = 2;
break;
default:
LIB_TRACE("no PINMAP found\r\n");
break;
}
return pq->ip;
}
/**
* @brief 设置RTC的时间
* @param datetime :时间戳结构
* @retval None
*/
void RTC_SetDateTime(RTC_DateTime_Type * datetime)
{
uint32_t i;
if(!datetime)
{
return;
}
RTC_DateTimeToSecond(datetime, &i);
LIB_TRACE("Reconfig:%d %s\r\n", i, __func__);
RTC->SR &= ~RTC_SR_TCE_MASK;
RTC->TSR = RTC_TSR_TSR(i);
RTC->SR |= RTC_SR_TCE_MASK;
}
/**
* \brief i2c bus scan test
* @param[in] MAP I2C引脚配置缩略图,详见i2c.h
* \retval None
*/
void I2C_Scan(uint32_t MAP)
{
uint8_t i;
uint8_t ret;
uint32_t instance;
instance = I2C_QuickInit(MAP, 100*1000);
for(i = 1; i < 127; i++)
{
ret = I2C_Probe(instance , i);
if(!ret)
{
LIB_TRACE("ADDR:0x%2X(7BIT) | 0x%2X(8BIT) found!\r\n", i, i<<1);
}
}
}
uint32_t FLASH_Test(uint32_t startAddr, uint32_t size)
{
int addr, i,err;
uint8_t *p;
uint8_t buf[SECTOR_SIZE];
FLASH_Init();
for(i=0;i<SECTOR_SIZE;i++)
{
buf[i] = i % 0xFF;
}
for (addr = startAddr; addr<size; addr+=SECTOR_SIZE)
{
LIB_TRACE("program addr:0x%X ...", addr);
err = FLASH_EraseSector(addr);
err += FLASH_WriteSector(addr, buf, SECTOR_SIZE);
if(err)
{
LIB_TRACE("issue command failed\r\n");
return 1;
}
p = (uint8_t*)addr;
LIB_TRACE("varify addr:0x%X ...", addr);
for(i=0;i<SECTOR_SIZE;i++)
{
if(*p++ != (i%0xFF))
{
err++;
LIB_TRACE("ERR:[%d]:0x%02X ", i, *p);
}
}
if(!err)
LIB_TRACE("OK\r\n");
else
LIB_TRACE("ERR\r\n");
}
return err;
}
void assert_failed(char * file, uint32_t line)
{
LIB_TRACE("assert failed @ %s in %d\r\n", file, line);
//����ʧ�ܼ��
while(1);
}
/**
* \brief dspi_hal_set_baud,Internal function
* \details Set the DSPI baud rate in bits per second.
* This function will take in the desired bitsPerSec (baud rate) and will calculate the nearest
* possible baud rate without exceeding the desired baud rate, and will return the calculated
* baud rate in bits-per-second. It requires that the caller also provide the frequency of the
* module source clock (in Hz).
*/
static uint32_t dspi_hal_set_baud(uint32_t instance, uint8_t whichCtar, uint32_t bitsPerSec, uint32_t sourceClockInHz)
{
uint32_t prescaler, bestPrescaler;
uint32_t scaler, bestScaler;
uint32_t dbr, bestDbr;
uint32_t realBaudrate, bestBaudrate;
uint32_t diff, min_diff;
uint32_t baudrate = bitsPerSec;
/* for master mode configuration, if slave mode detected, return 0*/
if(!(SPI_InstanceTable[instance]->MCR & SPI_MCR_MSTR_MASK))
{
return 0;
}
/* find combination of prescaler and scaler resulting in baudrate closest to the */
/* requested value */
min_diff = 0xFFFFFFFFU;
bestPrescaler = 0;
bestScaler = 0;
bestDbr = 1;
bestBaudrate = 0; /* required to avoid compilation warning */
/* In all for loops, if min_diff = 0, the exit for loop*/
for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++)
{
for (scaler = 0; (scaler < 16) && min_diff; scaler++)
{
for (dbr = 1; (dbr < 3) && min_diff; dbr++)
{
realBaudrate = ((sourceClockInHz * dbr) /
(s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler])));
/* calculate the baud rate difference based on the conditional statement*/
/* that states that the calculated baud rate must not exceed the desired baud rate*/
if (baudrate >= realBaudrate)
{
diff = baudrate-realBaudrate;
if (min_diff > diff)
{
/* a better match found */
min_diff = diff;
bestPrescaler = prescaler;
bestScaler = scaler;
bestBaudrate = realBaudrate;
bestDbr = dbr;
}
}
}
}
}
uint32_t temp;
/* write the best dbr, prescalar, and baud rate scalar to the CTAR*/
temp = SPI_InstanceTable[instance]->CTAR[whichCtar];
temp &= ~(SPI_CTAR_DBR_MASK| SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK);
if((bestDbr-1))
{
temp |= SPI_CTAR_DBR_MASK|SPI_CTAR_PBR(bestPrescaler)|SPI_CTAR_BR(bestScaler);
}
else
{
temp |= SPI_CTAR_PBR(bestPrescaler)|SPI_CTAR_BR(bestScaler);
}
SPI_InstanceTable[instance]->CTAR[whichCtar] = temp;
/* return the actual calculated baud rate*/
LIB_TRACE("bestBaudrate:%d\r\n", bestBaudrate);
return bestBaudrate;
}
/**
* @brief 初始化PWM波产生
* @code
*
* //TPM0_CH0_PE24 使用FTM0模块通道0 引脚E24上产生1KHz PWM波
* FTM_PWM_QuickInit(TPM0_CH0_PE24, 1000);
* @endcode
* @param MAP : 快速初始化通道
* @param frequencyInHZ : 频率
* @retval None
*/
uint8_t TPM_PWM_QuickInit(uint32_t MAP, TPM_PWM_Mode_Type mode, uint32_t req)
{
uint8_t i;
uint32_t modulo;
uint32_t clock;
int32_t pres;
uint8_t ps = 0;
QuickInit_Type * pq = (QuickInit_Type*)&(MAP);
/* init pinmux */
for(i = 0; i < pq->io_offset; i++)
{
PORT_PinMuxConfig(pq->io_instance, pq->io_base + i, (PORT_PinMux_Type) pq->mux);
}
/* calc req and ps */
uint32_t min_val = 0xFFFF;
/* cal ps */
CLOCK_GetClockFrequency(kMCGOutClock, &clock);
// if(MCG->C6 & MCG_C6_PLLS_MASK) /* PLL */
// {
// clock /= 2;
// }
// else /* FLL */
// {
//
// }
LIB_TRACE("%s %d\r\n", __func__, clock);
pres = (clock/req)/TPM_MOD_MOD_MASK;
if((clock/req)/pres > TPM_MOD_MOD_MASK)
{
pres++;
}
for(i = 0; i < 7; i++)
{
if((ABS(pres - (1<<i))) < min_val)
{
ps = i;
min_val = ABS(pres - (1<<i));
}
}
if(pres > (1<<ps)) ps++;
if(ps > 7) ps = 7;
modulo = ((clock/(1<<ps))/req) - 1;
LIB_TRACE("input frequency:%dHz\r\n", req);
LIB_TRACE("input clk:%d\r\n", clock);
LIB_TRACE("ps:%d\r\n", pres);
LIB_TRACE("modulo:%d\r\n", modulo);
LIB_TRACE("ip_instance:%d\r\n", pq->ip_instance);
LIB_TRACE("io_instance:%d\r\n", pq->io_instance);
LIB_TRACE("io_base:%d\r\n", pq->io_base);
LIB_TRACE("io_offset:%d\r\n", pq->io_offset);
LIB_TRACE("chl:%d\r\n", pq->channel);
_TPM_InitBasic(pq->ip_instance, modulo, (TPM_ClockDiv_Type)ps);
/* set FTM mode */
switch(mode)
{
case kPWM_EdgeAligned:
TPM_SetMode(pq->ip_instance, pq->channel, kTPM_Mode_EdgeAligned);
break;
default:
LIB_TRACE("error in FTM_PWM_Init\r\n");
break;
}
/* set duty to 50% */
TPM_PWM_ChangeDuty(pq->ip_instance, pq->channel, 5000);
return pq->ip_instance;
}
int ili9320_init(void)
{
int ret;
ret = 1;
uint32_t gpio_instance;
/* ??flexbus???? ?????? ?????????? */
/* Flexbus Init */
SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK);
/*control signals */
PORTB->PCR[19] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_OE
PORTD->PCR[1] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // CS0
PORTA->PCR[26] = PORT_PCR_MUX(6)|PORT_PCR_DSE_MASK; // A27
PORTC->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_BE_23_16
/*
PORTB->PCR[18] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD15
PORTC->PCR[0] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD14
PORTC->PCR[1] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD13
PORTC->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD12
PORTC->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD11
PORTC->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD10
PORTC->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD9
PORTC->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD8
PORTC->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD7
PORTC->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD6
PORTC->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD5
PORTD->PCR[2] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD4
PORTD->PCR[3] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD3
PORTD->PCR[4] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD2
PORTD->PCR[5] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD1
PORTD->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD0
*/
PORTB->PCR[17] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD16
PORTB->PCR[16] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD17
PORTB->PCR[11] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD18
PORTB->PCR[10] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD19
PORTB->PCR[9] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD20
PORTB->PCR[8] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD21
PORTB->PCR[7] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD22
PORTB->PCR[6] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD23
PORTC->PCR[15] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD24
PORTC->PCR[14] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD25
PORTC->PCR[13] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD26
PORTC->PCR[12] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD27
PORTB->PCR[23] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD28
PORTB->PCR[22] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD29
PORTB->PCR[21] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD30
PORTB->PCR[20] = PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK; // FB_AD31
FLEXBUS_InitTypeDef FLEXBUS_InitStruct;
FLEXBUS_InitStruct.ADSpaceMask = 0x800;
FLEXBUS_InitStruct.autoAckMode = kFLEXBUS_AutoAckEnable;
FLEXBUS_InitStruct.CSn = kFLEXBUS_CS0;
FLEXBUS_InitStruct.dataAlignMode = kFLEXBUS_DataLeftAligned;
FLEXBUS_InitStruct.dataWidth = kFLEXBUS_PortSize_16Bit;
FLEXBUS_InitStruct.baseAddress = ILI9320_BASE;
FLEXBUS_InitStruct.ByteEnableMode = kFLEXBUS_BE_AssertedWrite;
FLEXBUS_InitStruct.div = 1;
FLEXBUS_Init(&FLEXBUS_InitStruct);
FLEXBUS_PortMuxConfig(kFLEXBUS_CSPMCR_Group3, kFLEXBUS_CSPMCR_GROUP3_BE_23_16);
/* advanced config */
FLEXBUS_AdvancedConfigTypeDef config;
config.kFLEXBUS_brustWriteEnable = false;
config.kFLEXBUS_brustReadEnable = false;
config.kFLEXBUS_EXTS = true;
config.kFLEXBUS_ASET = 2;
config.kFLEXBUS_RDAH = 2;
config.kFLEXBUS_WRAH = 2;
config.kFLEXBUS_WS = 6;
FLEXBUS_AdvancedConfig(FLEXBUS_InitStruct.CSn, &config);
/* Back light */
gpio_instance = GPIO_QuickInit(HW_GPIOC, 3, kGPIO_Mode_OPP);
GPIO_WriteBit(gpio_instance, 3, 1);
/* reset */
gpio_instance = GPIO_QuickInit(HW_GPIOC, 19, kGPIO_Mode_OPP);
GPIO_WriteBit(gpio_instance, 19, 0);
DelayMs(5);
GPIO_WriteBit(gpio_instance, 19, 1);
DelayMs(5);
lcd_dev.id = ili9320_get_id();
switch(lcd_dev.id)
{
case 0x9341:
lcd_dev.cmd_setx = 0x2A;
lcd_dev.cmd_sety = 0x2B;
lcd_dev.cmd_gram = 0x2C;
WR_CMD(PWCTLB);
WR_DATA(0x00);
WR_DATA(0x81);
WR_DATA(0x30);
WR_CMD(PWONSCTL);
WR_DATA(0x64);
WR_DATA(0x03);
WR_DATA(0x12);
WR_DATA(0x81);
WR_CMD(DTIMCTLA);
WR_DATA(0x85);
WR_DATA(0x10);
WR_DATA(0x78);
WR_CMD(PWCTLA);
WR_DATA(0x39);
WR_DATA(0x2C);
WR_DATA(0x00);
WR_DATA(0x34);
WR_DATA(0x02);
WR_CMD(PRCTL);
WR_DATA(0x20);
WR_CMD(DTIMCTLB);
WR_DATA(0x00);
WR_DATA(0x00);
WR_CMD(FRMCTR1);
WR_DATA(0x00);
WR_DATA(0x1B);
WR_CMD(DISCTRL);
WR_DATA(0x0A);
WR_DATA(0xA2);
WR_CMD(PWCTRL1);
WR_DATA(0x35);
WR_CMD(PWCTRL2);
WR_DATA(0x11);
WR_CMD(VMCTRL1);
WR_DATA(0x45);
WR_DATA(0x45);
WR_CMD(VMCTRL2);
WR_DATA(0xA2);
WR_CMD(EN3G);
WR_DATA(0x00);
WR_CMD(GAMSET);
WR_DATA(0x01);
WR_CMD(PGAMCTRL);
WR_DATA(0x0F);
WR_DATA(0x26);
WR_DATA(0x24);
WR_DATA(0x0B);
WR_DATA(0x0E);
WR_DATA(0x09);
WR_DATA(0x54);
WR_DATA(0xA8);
WR_DATA(0x46);
WR_DATA(0x0C);
WR_DATA(0x17);
WR_DATA(0x09);
WR_DATA(0x0F);
WR_DATA(0x07);
WR_DATA(0x00);
WR_CMD(NGAMCTRL);
WR_DATA(0x00);
WR_DATA(0x19);
WR_DATA(0x1B);
WR_DATA(0x04);
WR_DATA(0x10);
WR_DATA(0x07);
WR_DATA(0x2A);
WR_DATA(0x47);
WR_DATA(0x39);
WR_DATA(0x03);
WR_DATA(0x06);
WR_DATA(0x06);
WR_DATA(0x30);
WR_DATA(0x38);
WR_DATA(0x0F);
WR_CMD(MADCTL);
WR_DATA(0x08);
WR_CMD(CASET);
WR_DATA(0x00);
WR_DATA(0x00);
WR_DATA(0x00);
WR_DATA(0xEF);
WR_CMD(PASET);
WR_DATA(0x00);
WR_DATA(0x00);
WR_DATA(0x01);
WR_DATA(0x3F);
WR_CMD(PIXSET);
WR_DATA(0x05);
WR_CMD(SLPOUT);
DelayMs(50);
WR_CMD(DISPON);
break;
case 0x9320:
lcd_dev.cmd_setx = 0x20;
lcd_dev.cmd_sety = 0x21;
lcd_dev.cmd_gram = 0x22;
write_reg(0xe5,0x8000); // Set the internal vcore voltage
write_reg(0x00,0x0001); // start OSC
write_reg(0x2b,0x0010); //Set the frame rate as 80 when the internal resistor is used for oscillator circuit
write_reg(0x01,0x0100); //s720 to s1 ; G1 to G320
write_reg(0x02,0x0700); //set the line inversion
//WR_CMD(0x03,0x1018); //65536 colors
write_reg(0x03,0x1030);
//??
#ifdef LCD_USE_HORIZONTAL
write_reg(0x03,(0<<5)|(0<<4)|(1<<3)|(1<<12));
#else
write_reg(0x03,(1<<5)|(1<<4)|(0<<3)|(1<<12));
#endif
write_reg(0x04,0x0000);
write_reg(0x08,0x0202);
write_reg(0x09,0x0000);
write_reg(0x0a,0x0000);
write_reg(0x0c,0x0000);
write_reg(0x0d,0x0000);
write_reg(0x0f,0x0000);
write_reg(0x50,0x0000);
write_reg(0x51,0x00ef);
write_reg(0x52,0x0000);
write_reg(0x53,0x013f);
write_reg(0x60,0x2700);
write_reg(0x61,0x0001);
write_reg(0x6a,0x0000);
write_reg(0x80,0x0000);
write_reg(0x81,0x0000);
write_reg(0x82,0x0000);
write_reg(0x83,0x0000);
write_reg(0x84,0x0000);
write_reg(0x85,0x0000);
write_reg(0x90,0x0010);
write_reg(0x92,0x0000);
write_reg(0x93,0x0003);
write_reg(0x95,0x0110);
write_reg(0x97,0x0000);
write_reg(0x98,0x0000);
write_reg(0x10,0x0000);
write_reg(0x11,0x0000);
write_reg(0x12,0x0000);
write_reg(0x13,0x0000);
DelayMs(5);
write_reg(0x10,0x17b0);
write_reg(0x11,0x0004);
;
write_reg(0x12,0x013e);
;
write_reg(0x13,0x1f00);
write_reg(0x29,0x000f);
;
write_reg(0x20,0x0000);
write_reg(0x21,0x0000);
write_reg(0x30,0x0204);
write_reg(0x31,0x0001);
write_reg(0x32,0x0000);
write_reg(0x35,0x0206);
write_reg(0x36,0x0600);
write_reg(0x37,0x0500);
write_reg(0x38,0x0505);
write_reg(0x39,0x0407);
write_reg(0x3c,0x0500);
write_reg(0x3d,0x0503);
write_reg(0x07,0x0173);
ret = 0;
break;
case 0x8989:
lcd_dev.cmd_setx =0x4e;
lcd_dev.cmd_sety =0x4f;
lcd_dev.cmd_gram =0x22;
write_reg(0x0000,0x0001);
write_reg(0x0003,0xA8A4);
write_reg(0x000C,0x0000);
write_reg(0x000D,0x080C);
write_reg(0x000E,0x2B00);
write_reg(0x001E,0x00B0);
write_reg(0x0001,0x2B3F);
write_reg(0x0002,0x0600);
write_reg(0x0010,0x0000);
write_reg(0x0011,0x6070);
write_reg(0x0005,0x0000);
write_reg(0x0006,0x0000);
write_reg(0x0016,0xEF1C);
write_reg(0x0017,0x0003);
write_reg(0x0007,0x0233);
write_reg(0x000B,0x0000);
write_reg(0x000F,0x0000);
write_reg(0x0041,0x0000);
write_reg(0x0042,0x0000);
write_reg(0x0048,0x0000);
write_reg(0x0049,0x013F);
write_reg(0x004A,0x0000);
write_reg(0x004B,0x0000);
write_reg(0x0044,0xEF00);
write_reg(0x0045,0x0000);
write_reg(0x0046,0x013F);
write_reg(0x0030,0x0707);
write_reg(0x0031,0x0204);
write_reg(0x0032,0x0204);
write_reg(0x0033,0x0502);
write_reg(0x0034,0x0507);
write_reg(0x0035,0x0204);
write_reg(0x0036,0x0204);
write_reg(0x0037,0x0502);
write_reg(0x003A,0x0302);
write_reg(0x003B,0x0302);
write_reg(0x0023,0x0000);
write_reg(0x0024,0x0000);
write_reg(0x0025,0x8000);
write_reg(0x004f,0);
write_reg(0x004e,0);
ret = 0;
break;
default:
break;
}
LIB_TRACE("LCD CONTROLLER ID:0x%X\r\n", ili9320_get_id());
ili9320_clear(BLACK);
return ret;
}
