static inline int stm32_clock_control_on(struct device *dev, clock_control_subsys_t sub_system) { struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system); ARG_UNUSED(dev); switch (pclken->bus) { case STM32_CLOCK_BUS_AHB1: LL_AHB1_GRP1_EnableClock(pclken->enr); break; #if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F4X) case STM32_CLOCK_BUS_AHB2: LL_AHB2_GRP1_EnableClock(pclken->enr); break; #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X */ case STM32_CLOCK_BUS_APB1: LL_APB1_GRP1_EnableClock(pclken->enr); break; #if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F0X) case STM32_CLOCK_BUS_APB1_2: LL_APB1_GRP2_EnableClock(pclken->enr); break; #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */ #ifndef CONFIG_SOC_SERIES_STM32F0X case STM32_CLOCK_BUS_APB2: LL_APB2_GRP1_EnableClock(pclken->enr); break; #endif /* CONFIG_SOC_SERIES_STM32F0X */ } return 0; }
static int iwdg_stm32_setup(struct device *dev, u8_t options) { IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev); /* Deactivate running when debugger is attached. */ if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) { #if defined(CONFIG_SOC_SERIES_STM32F0X) LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU); #elif defined(CONFIG_SOC_SERIES_STM32L0X) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU); #endif LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP); } if (options & WDT_OPT_PAUSE_IN_SLEEP) { return -ENOTSUP; } LL_IWDG_Enable(iwdg); return 0; }