/** * @brief Set TIMx registers to their reset values. * @param TIMx Timer instance * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(TIMx)); if (TIMx == TIM2) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } #if defined(TIM3) else if (TIMx == TIM3) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); } #endif /* TIM3 */ #if defined(TIM6) else if (TIMx == TIM6) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); } #endif /* TIM6 */ #if defined(TIM7) else if (TIMx == TIM7) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); } #endif /* TIM7 */ else if (TIMx == TIM21) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM21); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM21); } #if defined(TIM22) else if (TIMx == TIM22) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM22); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM22); } #endif /* TIM22 */ else { result = ERROR; } return result; }
/** * @brief De-initialize the SPI registers to their default reset values. * @param SPIx SPI Instance * @retval An ErrorStatus enumeration value: * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_SPI_ALL_INSTANCE(SPIx)); #if defined(SPI1) if (SPIx == SPI1) { /* Force reset of SPI clock */ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); /* Release reset of SPI clock */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); status = SUCCESS; } #endif /* SPI1 */ #if defined(SPI2) if (SPIx == SPI2) { /* Force reset of SPI clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); /* Release reset of SPI clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); status = SUCCESS; } #endif /* SPI2 */ return status; }
/** * @brief De-initialize USART registers (Registers restored to their default values). * @param USARTx USART Instance * @retval An ErrorStatus enumeration value: * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_UART_INSTANCE(USARTx)); if (USARTx == USART1) { /* Force reset of USART clock */ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); /* Release reset of USART clock */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); } else if (USARTx == USART2) { /* Force reset of USART clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); /* Release reset of USART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); } #if defined(USART3) else if (USARTx == USART3) { /* Force reset of USART clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); /* Release reset of USART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); } #endif /* USART3 */ #if defined(UART4) else if (USARTx == UART4) { /* Force reset of UART clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); /* Release reset of UART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); } #endif /* UART4 */ #if defined(UART5) else if (USARTx == UART5) { /* Force reset of UART clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); /* Release reset of UART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); } #endif /* UART5 */ else { status = ERROR; } return (status); }
/** * @brief De-initialize GPIO registers (Registers restored to their default values). * @param GPIOx GPIO Port * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); /* Force and Release reset on clock of GPIOx Port */ if (GPIOx == GPIOA) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA); } else if (GPIOx == GPIOB) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB); } else if (GPIOx == GPIOC) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC); } else if (GPIOx == GPIOD) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD); } #if defined(GPIOE) else if (GPIOx == GPIOE) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE); } #endif #if defined(GPIOF) else if (GPIOx == GPIOF) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF); } #endif #if defined(GPIOG) else if (GPIOx == GPIOG) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG); } #endif else { status = ERROR; } return (status); }
/** * @brief Set HRTIM instance registers to their reset values. * @param HRTIMx High Resolution Timer instance * @retval ErrorStatus enumeration value: * - SUCCESS: HRTIMx registers are de-initialized * - ERROR: invalid HRTIMx instance */ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx) { ErrorStatus result = SUCCESS; /* Check the parameters */ assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx)); LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1); return result; }
/** * @brief De-initialize registers of all ADC instances belonging to * the same ADC common instance to their default reset values. * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); /* Force reset of ADC clock (core clock) */ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); /* Release reset of ADC clock (core clock) */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); return SUCCESS; }