/**
* Hook before the probe filter initialization sequence.
*
* @param[in] HtAssistServices HT Assist family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10HookBeforeInit (
IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 PciRegister;
UINT32 PfCtrlRegister;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID LogicalId;
AGESA_STATUS IgnoredStatus;
UINT32 PackageType;
GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
PackageType = LibAmdGetPackageType (StdHeader);
PciRegister = 0;
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFWayNum = 2;
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFSubCacheEn = 15;
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFLoIndexHashEn = 1;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFPreferredSORepl =
((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
// Assumption: all socket use the same CPU package.
if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {
// Apply erratum #384
// Set F2x11C[13:12] = 11b
PciAddress.Address.Function = FUNC_2;
PciAddress.Address.Register = 0x11C;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
PciRegister |= 0x3000;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
}
}
}
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps
* appropriate for the executing Rev D core.
*
* @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[out] Table Table of appropriate init steps for the executing core.
* @param[in] EarlyParams Service Interface structure to initialize.
* @param[in] StdHeader Opaque handle to standard config header.
*
*/
VOID
GetF10HyEarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 ProcessorPackageType;
CPU_LOGICAL_ID LogicalId;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
ProcessorPackageType = LibAmdGetPackageType (StdHeader);
// Check if this CPU is affected by erratum 419.
if (((LogicalId.Revision & AMD_F10_HY_SCM_D0) != 0) && ((ProcessorPackageType & (PACKAGE_TYPE_G34 | PACKAGE_TYPE_FR2_FR5_FR6)) == 0)) {
// Return initialization steps such that the microcode patch is applied before
// brand string determination is performed.
*Table = F10HyC32D0EarlyInitOnCoreTable;
} else {
// No workaround is necessary. Return the standard table.
GetF10EarlyInitOnCoreTable (FamilyServices, Table, EarlyParams, StdHeader);
}
}
/**
* Family 10h core 0 entry point for performing power plane initialization.
*
* The steps are as follows:
* 1. If single plane, program lower VID code of CpuVid & NbVid for all
* enabled P-States.
* 2. Configure F3xA0[SlamMode] & F3xD8[VsRampTime & VsSlamTime] based on
* platform requirements.
* 3. Configure F3xD4[PowerStepUp & PowerStepDown]
* 4. Optionally configure F3xA0[PsiVidEn & PsiVid]
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10CpuAmdPmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN PviModeFlag;
PCI_ADDR PciAddress;
UINT16 PowerStepTime;
UINT32 PowerStepEncoded;
UINT32 LocalPciRegister;
UINT32 VsSlamTime;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 NumOfCores;
UINT32 LowCore;
UINT32 AndMask;
UINT32 OrMask;
UINT32 ProcessorPackageType;
UINT64 LocalMsrRegister;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PLATFORM_FEATS Features;
CPU_LOGICAL_ID LogicalId;
// Initialize the union
Features.PlatformValue = 0;
GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader);
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
ASSERT (Core == 0);
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
// Set SlamVidMode
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = PW_CTL_MISC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
AndMask = 0xFFFFFFFF;
OrMask = 0x00000000;
if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 1) {
PviModeFlag = TRUE;
((POWER_CTRL_MISC_REGISTER *) &AndMask)->SlamVidMode = 0;
// Have all single plane cores adjust their NB and CPU VID fields
TaskPtr.FuncAddress.PfApTask = F10PmPwrPlaneInitPviCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
} else {
PviModeFlag = FALSE;
((POWER_CTRL_MISC_REGISTER *) &OrMask)->SlamVidMode = 1;
}
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
// Configure PowerStepUp/PowerStepDown
PciAddress.Address.Register = CPTC0_REG;
if ((Features.PlatformFeatures.PlatformSingleLink == 1) ||
(Features.PlatformFeatures.PlatformUma == 1) ||
(Features.PlatformFeatures.PlatformUmaIfcm == 1) ||
(Features.PlatformFeatures.PlatformIfcm == 1) ||
(Features.PlatformFeatures.PlatformIommu == 1)) {
PowerStepEncoded = 0x8;
} else {
GetGivenModuleCoreRange ((UINT32) Socket,
(UINT32) Module,
&LowCore,
&NumOfCores,
StdHeader);
NumOfCores = ((NumOfCores - LowCore) + 1);
PowerStepTime = (UINT16) (400 / NumOfCores);
for (PowerStepEncoded = 0xF; PowerStepEncoded > 0; PowerStepEncoded--) {
if (PowerStepTime <= PowerStepEncodings[PowerStepEncoded]) {
break;
}
}
}
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = PowerStepEncoded;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = PowerStepEncoded;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
if ((LogicalId.Revision & AMD_F10_C3) != 0) {
// Set up Pop up P-state register
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
AndMask = 0xFFFFFFFF;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupPstate = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuVid = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuFid = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuDid = 0;
OrMask = 0x00000000;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal;
LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal + PS_REG_BASE), &LocalMsrRegister, StdHeader);
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->CpuVid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid;
PciAddress.Address.Register = POPUP_PSTATE_REG;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Set AltVidStart
PciAddress.Address.Register = CPTC1_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->CpuVid;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Set up Altvid slam time
ProcessorPackageType = LibAmdGetPackageType (StdHeader);
PciAddress.Address.Register = CPTC2_REG;
VsSlamTime = F10CalculateAltvidVSSlamTimeOnCore (PviModeFlag, &PciAddress, CpuEarlyParams, StdHeader);
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->AltvidVSSlamTime = 0;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->SlamTimeMode = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->AltvidVSSlamTime = VsSlamTime;
if (ProcessorPackageType == PACKAGE_TYPE_S1G3_S1G4 || ProcessorPackageType == PACKAGE_TYPE_ASB2) {
// If CPUID Fn8000_0001_EBX[PkgType]=0010b or 0100b, BIOS should program this to 10b;
// else BIOS should leave this field at 00b.
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->SlamTimeMode = 2;
}
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
}
if (IsWarmReset (StdHeader) && !PviModeFlag) {
// Configure PsiVid
F10PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader);
}
}
AGESA_STATUS
GnbEnvInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AMD_ENV_PARAMS *EnvParamsPtr;
UINT32 Property;
GNB_HANDLE *GnbHandle;
D18F5x170_STRUCT D18F5x170;
D0F0xBC_x1F8DC_STRUCT D0F0xBC_x1F8DC;
PP_FUSE_ARRAY *PpFuseArray;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Enter\n");
Property = TABLE_PROPERTY_DEFAULT;
EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader;
GnbHandle = GnbGetHandle (StdHeader);
ASSERT (GnbHandle != NULL);
GnbLoadFuseTableTN (StdHeader);
Status = GnbSetTom (GnbGetHostPciAddress (GnbHandle), StdHeader);
GnbOrbDynamicWake (GnbGetHostPciAddress (GnbHandle), StdHeader);
GnbClumpUnitIdV4 (GnbHandle, StdHeader);
GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader);
Property |= GnbBuildOptionsTN.CfgLoadlineEnable ? TABLE_PROPERTY_LOADLINE_ENABLE : 0;
if (!EnvParamsPtr->GnbEnvConfiguration.IommuSupport) {
Property |= TABLE_PROPERTY_IOMMU_DISABLED;
} else {
// Force disable iommu if non-FM2
// PACKAGE_TYPE_FP2 1
// PACKAGE_TYPE_FS1r2 2
// PACKAGE_TYPE_FM2 4
if (LibAmdGetPackageType (StdHeader) != PACKAGE_TYPE_FM2) {
EnvParamsPtr->GnbEnvConfiguration.IommuSupport = FALSE;
Property |= TABLE_PROPERTY_IOMMU_DISABLED;
} else {
Property |= GnbBuildOptionsTN.GnbCommonOptions.CfgIommuL1ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING : 0;
Property |= GnbBuildOptionsTN.GnbCommonOptions.CfgIommuL2ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING : 0;
}
}
if (GnbBuildOptionsTN.CfgNbdpmEnable) {
GnbRegisterReadTN (
TYPE_D18F5,
D18F5x170_ADDRESS,
&D18F5x170.Value,
0,
StdHeader
);
// Check if NbPstate enable
if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) {
Property |= TABLE_PROPERTY_NBDPM;
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
if (PpFuseArray != NULL) {
// NBDPM is requesting SclkVid0 from the register.
// Write them back if SclkVid has been changed in PpFuseArray.
GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, 0, StdHeader);
if ((D0F0xBC_x1F8DC.Field.SClkVid0 != PpFuseArray->SclkVid[0]) ||
(D0F0xBC_x1F8DC.Field.SClkVid1 != PpFuseArray->SclkVid[1]) ||
(D0F0xBC_x1F8DC.Field.SClkVid2 != PpFuseArray->SclkVid[2]) ||
(D0F0xBC_x1F8DC.Field.SClkVid3 != PpFuseArray->SclkVid[3])) {
D0F0xBC_x1F8DC.Field.SClkVid0 = PpFuseArray->SclkVid[0];
D0F0xBC_x1F8DC.Field.SClkVid1 = PpFuseArray->SclkVid[1];
D0F0xBC_x1F8DC.Field.SClkVid2 = PpFuseArray->SclkVid[2];
D0F0xBC_x1F8DC.Field.SClkVid3 = PpFuseArray->SclkVid[3];
GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
}
}
}
}
IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEnvInitTableTN,
Property,
GNB_TABLE_FLAGS_FORCE_S3_SAVE,
StdHeader
);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Exit [0x%x]\n", Status);
return Status;
}
