STATIC VOID
IdsPerfSaveReg (
IN OUT PERFREGBACKUP * perfreg,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdMsrRead (0xC001100A, &perfreg->SMsr, StdHeader);
LibAmdReadCpuReg (DR0_REG, &perfreg->Dr0Reg);
LibAmdReadCpuReg (DR7_REG, &perfreg->Dr7Reg);
LibAmdReadCpuReg (CR4_REG, &perfreg->Cr4Reg);
}
/**
* Output Test Point function .
*
* @param[in,out] StdHeader The Pointer of Standard Header.
*
* @retval AGESA_SUCCESS Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
* @retval AGESA_ERROR Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
*
**/
AGESA_STATUS
IdsPerfAnalyseTimestamp (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS status;
LOCATE_HEAP_PTR LocateHeapStructPtr;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
IDS_CALLOUT_STRUCT IdsCalloutData;
AGESA_STATUS Status;
PERFREGBACKUP PerfReg;
UINT32 CR4reg;
UINT64 SMsr;
LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status != AGESA_SUCCESS) {
return status;
}
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->Version = IDS_PERF_VERSION;
IdsCalloutData.IdsNvPtr = NULL;
IdsCalloutData.StdHeader = *StdHeader;
IdsCalloutData.Reserved = 0;
Status = AgesaGetIdsData (IDS_CALLOUT_GET_PERF_BUFFER, &IdsCalloutData);
//Check if Platform BIOS provide a buffer to copy
if ((Status == AGESA_SUCCESS) && (IdsCalloutData.Reserved != 0)) {
LibAmdMemCopy ((VOID *)IdsCalloutData.Reserved, LocateHeapStructPtr.BufferPtr, sizeof (TP_Perf_STRUCT), StdHeader);
} else {
//No platform performance buffer provide, use the default HDTOUT output
if (AmdIdsHdtOutSupport () == FALSE) {
//Init break point
IdsPerfSaveReg (&PerfReg, StdHeader);
LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
SMsr |= 1;
LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
LibAmdWriteCpuReg (DR2_REG, 0x99cc);
LibAmdWriteCpuReg (DR7_REG, 0x02000420);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
IdsPerfHdtOut (1, (UINT32) (UINT64) LocateHeapStructPtr.BufferPtr, StdHeader);
IdsPerfRestoreReg (&PerfReg, StdHeader);
}
}
return status;
}
/**
* Determine whether IDS console is enabled.
*
* @param[in,out] IdsConsole The Pointer of Ids console data
*
* @retval TRUE Ids console is enabled.
* @retval FALSE Ids console is disabled.
*
**/
BOOLEAN
AmdIdsHdtOutSupport (
VOID
)
{
BOOLEAN Result;
UINT32 DR2reg;
Result = FALSE;
LibAmdReadCpuReg (DR2_REG, &DR2reg);
if (DR2reg == 0x99CC) {
Result = TRUE;
}
return Result;
}
/**
* Determine whether IDS console is enabled.
*
* @param[in,out] pHdtoutHeader Address of hdtout header pointer
* @param[in,out] StdHeader The Pointer of AGESA Header
*
* @retval TRUE pHdtoutHeader Non zero
* @retval FALSE pHdtoutHeader is NULL
*
**/
STATIC BOOLEAN
AmdIdsHdtoutGetHeader (
IN OUT HDTOUT_HEADER **pHdtoutHeaderPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Dr3Reg;
HDTOUT_HEADER *HdtoutHeaderPtr;
LibAmdReadCpuReg (DR3_REG, &Dr3Reg);
HdtoutHeaderPtr = (HDTOUT_HEADER *) (UINTN) Dr3Reg;
if ((HdtoutHeaderPtr != NULL) && (HdtoutHeaderPtr->Signature == HDTOUT_HEADER_SIGNATURE)) {
*pHdtoutHeaderPtr = HdtoutHeaderPtr;
return TRUE;
} else {
return FALSE;
}
}
/**
*
* Restore register setting used for HDT out Function.
*
*
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
VOID
AmdIdsHdtOutRegisterInit (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CR4reg;
UINT64 SMsr;
SMsr |= 1;
LibAmdWriteCpuReg (DR2_REG, 0x99CC);
LibAmdWriteCpuReg (DR7_REG, 0x02000420);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
}
/**
*
* Initial register setting used for HDT out Function.
*
*
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
VOID
AmdIdsHdtOutRegisterRestore (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CR4reg;
UINT64 SMsr;
SMsr &= ~BIT0;
LibAmdWriteCpuReg (DR2_REG, 0);
LibAmdWriteCpuReg (DR3_REG, 0);
LibAmdWriteCpuReg (DR7_REG, 0);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg & (~BIT3));
}
/**
*
* Enable all the caches on current core.
*
* @param[in] ApExeParams Handle to config for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
EnableAllCaches (
IN AP_EXE_PARAMS *ApExeParams
)
{
UINT32 CR0Data;
L3_FEATURE_FAMILY_SERVICES *FamilyServices;
// Enable cache through CR0.
LibAmdReadCpuReg (0, &CR0Data);
CR0Data &= ~(0x60000000);
LibAmdWriteCpuReg (0, CR0Data);
GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (const VOID **) &FamilyServices, &ApExeParams->StdHeader);
FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader);
return AGESA_SUCCESS;
}
/**
*
* Initial register setting used for HDT out Function.
*
*
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
STATIC VOID
AmdIdsHdtOutRegisterRestore (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CR4reg;
UINT64 SMsr;
LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
SMsr &= ~BIT0;
LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
LibAmdWriteCpuReg (DR2_REG, 0);
LibAmdWriteCpuReg (DR3_REG, 0);
LibAmdWriteCpuReg (DR7_REG, 0);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg & (~BIT3));
}
VOID
MemRecTBeginTraining (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
S_UINT64 SMsr;
MEM_DATA_STRUCT *MemPtr;
MEM_NB_BLOCK *NBPtr;
NBPtr = TechPtr->NBPtr;
MemPtr = NBPtr->MemPtr;
LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg);
LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32) 1 << 9)); // enable SSE2
LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR
TechPtr->HwcrLo = SMsr.lo;
SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis
SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS
LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
}
/**
* Output Test Point function .
*
* @param[in,out] StdHeader The Pointer of Standard Header.
*
* @retval AGESA_SUCCESS Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
* @retval AGESA_ERROR Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
*
**/
AGESA_STATUS
IdsPerfAnalyseTimestamp (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS status;
LOCATE_HEAP_PTR LocateHeapStructPtr;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
PERFREGBACKUP PerfReg;
UINT32 CR4reg;
UINT64 SMsr;
LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status != AGESA_SUCCESS) {
return status;
}
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
//Init break point
IdsPerfSaveReg (&PerfReg, StdHeader);
LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
SMsr |= 1;
LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
LibAmdWriteCpuReg (DR0_REG, 0x8899);
LibAmdWriteCpuReg (DR7_REG, 0x00020402);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
IdsPerfHdtOut (1, (UINT32) LocateHeapStructPtr.BufferPtr, StdHeader);
IdsPerfRestoreReg (&PerfReg, StdHeader);
return status;
}
/**
*
* Disable all the caches on current core.
*
* @param[in] ApExeParams Handle to config for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
DisableAllCaches (
IN AP_EXE_PARAMS *ApExeParams
)
{
UINT32 CR0Data;
L3_FEATURE_FAMILY_SERVICES *FamilyServices;
// Disable cache through CR0.
LibAmdReadCpuReg (0, &CR0Data);
CR0Data |= (0x60000000);
LibAmdWriteCpuReg (0, CR0Data);
// Execute wbinvd
LibAmdWriteBackInvalidateCache ();
GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (const VOID **) &FamilyServices, &ApExeParams->StdHeader);
FamilyServices->HookDisableCache (FamilyServices, *(BOOLEAN *) ApExeParams->RelatedDataBlock, &ApExeParams->StdHeader);
return AGESA_SUCCESS;
}
