/*
* ======== InterruptEve_intShmStub ========
*/
Void InterruptEve_intShmStub(UArg arg)
{
InterruptEve_FxnTable *table;
/* Process messages from the HOST */
if ((REG32(MAILBOX_IRQENABLE_SET_EVE) & MAILBOX_REG_VAL(HOST_TO_EVE))
&& REG32(MAILBOX_STATUS(HOST_TO_EVE)) != 0) {
table = &(InterruptEve_module->fxnTable[0]);
(table->func)(table->arg);
}
/* Process messages from VIDEO OR VPSS */
if ((REG32(MAILBOX_IRQENABLE_SET_EVE) & MAILBOX_REG_VAL(VIDEO_TO_EVE))
&& REG32(MAILBOX_STATUS(VIDEO_TO_EVE)) != 0) {
table = &(InterruptEve_module->fxnTable[1]);
(table->func)(table->arg);
}
/* Process messages from DSP */
if ((REG32(MAILBOX_IRQENABLE_SET_EVE) & MAILBOX_REG_VAL(DSP_TO_EVE))
&& REG32(MAILBOX_STATUS(DSP_TO_EVE)) != 0) {
table = &(InterruptEve_module->fxnTable[2]);
(table->func)(table->arg);
}
}
/*
* ======== InterruptHost_intClear ========
* Clear interrupt
*/
UInt InterruptHost_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
if (remoteProcId == InterruptHost_dspProcId) { /* DSP */
arg = REG32(MAILBOX_MESSAGE(DSP_TO_HOST));
REG32(MAILBOX_IRQSTATUS_CLR_HOST) = MAILBOX_REG_VAL(DSP_TO_HOST);
}
else if (remoteProcId == InterruptHost_videoProcId) { /* VIDEO-M3 */
arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_HOST));
REG32(MAILBOX_IRQSTATUS_CLR_HOST) = MAILBOX_REG_VAL(VIDEO_TO_HOST);
}
else if (remoteProcId == InterruptHost_vpssProcId) { /* VPSS-M3 */
arg = REG32(MAILBOX_MESSAGE(VPSS_TO_HOST));
REG32(MAILBOX_IRQSTATUS_CLR_HOST) = MAILBOX_REG_VAL(VPSS_TO_HOST);
}
else { /* EVE */
arg = REG32(EVE_MAILBOX_MESSAGE(EVE_TO_HOST));
REG32(EVE_MAILBOX_IRQSTATUS_CLR_HOST) = MAILBOX_REG_VAL(EVE_TO_HOST);
/* Write to EOI (End Of Interrupt) register */
REG32(EVE_MAILBOX_EOI_REG) = 0x1;
}
return (arg);
}
/*
* ======== InterruptHost_intShmStub ========
*/
Void InterruptHost_intShmStub(UArg arg)
{
InterruptHost_FxnTable *table;
/* Process messages from the DSP */
if ((REG32(MAILBOX_IRQENABLE_SET_HOST) & MAILBOX_REG_VAL(DSP_TO_HOST))
&& REG32(MAILBOX_STATUS(DSP_TO_HOST)) != 0) {
table = &(InterruptHost_module->fxnTable[0]);
(table->func)(table->arg);
}
/* Process messages from VIDEO */
if ((REG32(MAILBOX_IRQENABLE_SET_HOST) & MAILBOX_REG_VAL(VIDEO_TO_HOST))
&& REG32(MAILBOX_STATUS(VIDEO_TO_HOST)) != 0) {
table = &(InterruptHost_module->fxnTable[1]);
(table->func)(table->arg);
}
/* Process messages from VPSS */
if ((REG32(MAILBOX_IRQENABLE_SET_HOST) & MAILBOX_REG_VAL(VPSS_TO_HOST))
&& REG32(MAILBOX_STATUS(VPSS_TO_HOST)) != 0) {
table = &(InterruptHost_module->fxnTable[2]);
(table->func)(table->arg);
}
}
/*!
* ======== InterruptDucati_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptDucati_intDisable(UInt16 remoteProcId,
IInterrupt_IntInfo *intInfo)
{
/*
* If the remote processor communicates via mailboxes, we should disable
* the Mailbox IRQ instead of disabling the Hwi because multiple mailboxes
* share the same Hwi
*/
if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
if (remoteProcId == InterruptDucati_hostProcId) {
REG32(MAILBOX_IRQENABLE_CLR_VIDEO) = MAILBOX_REG_VAL(HOST_TO_VIDEO);
}
else if (remoteProcId == InterruptDucati_dspProcId) {
REG32(MAILBOX_IRQENABLE_CLR_VIDEO) = MAILBOX_REG_VAL(DSP_TO_VIDEO);
}
else {
Hwi_disableInterrupt(M3INT);
}
}
else {
if (remoteProcId == InterruptDucati_hostProcId) {
REG32(MAILBOX_IRQENABLE_CLR_VPSS) = MAILBOX_REG_VAL(HOST_TO_VPSS);
}
else if (remoteProcId == InterruptDucati_dspProcId) {
REG32(MAILBOX_IRQENABLE_CLR_VPSS) = MAILBOX_REG_VAL(DSP_TO_VPSS);
}
else {
Hwi_disableInterrupt(M3INT);
}
}
}
/*!
* ======== InterruptDucati_intShmMbxStub ========
*/
Void InterruptDucati_intShmMbxStub(UArg arg)
{
InterruptDucati_FxnTable *table;
if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
if ((REG32(MAILBOX_IRQENABLE_SET_VIDEO) &
MAILBOX_REG_VAL(DSP_TO_VIDEO)) &&
REG32(MAILBOX_STATUS(DSP_TO_VIDEO)) != 0) { /* DSP to VIDEO-M3 */
table = &(InterruptDucati_module->fxnTable[0]);
(table->func)(table->arg);
}
if ((REG32(MAILBOX_IRQENABLE_SET_VIDEO) &
MAILBOX_REG_VAL(HOST_TO_VIDEO)) &&
REG32(MAILBOX_STATUS(HOST_TO_VIDEO)) != 0) { /* HOST to VIDEO-M3 */
table = &(InterruptDucati_module->fxnTable[1]);
(table->func)(table->arg);
}
}
else {
if ((REG32(MAILBOX_IRQENABLE_SET_VPSS) &
MAILBOX_REG_VAL(DSP_TO_VPSS)) &&
REG32(MAILBOX_STATUS(DSP_TO_VPSS)) != 0) { /* DSP to VPSS-M3 */
table = &(InterruptDucati_module->fxnTable[0]);
(table->func)(table->arg);
}
if ((REG32(MAILBOX_IRQENABLE_SET_VPSS) &
MAILBOX_REG_VAL(HOST_TO_VPSS)) &&
REG32(MAILBOX_STATUS(HOST_TO_VPSS)) != 0) { /* HOST to VPSS-M3 */
table = &(InterruptDucati_module->fxnTable[1]);
(table->func)(table->arg);
}
}
}
/*!
* ======== InterruptDucati_intClear ========
* Clear interrupt
*/
UInt InterruptDucati_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
if (remoteProcId == InterruptDucati_videoProcId ||
remoteProcId == InterruptDucati_vpssProcId) {
arg = REG32(InterruptDucati_ducatiCtrlBaseAddr);
/* Look at BIOS's ducati Core id */
if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
if ((REG16(INTERRUPT_VIDEO) & 0x1) == 0x1) {
/* VPSS-M3 to VIDEO-M3 */
REG16(INTERRUPT_VIDEO) &= ~(0x1);
}
}
else {
if ((REG16(INTERRUPT_VPSS) & 0x1) == 0x1) {
/* VIDEO-M3 to VPSS-M3 */
REG16(INTERRUPT_VPSS) &= ~(0x1);
}
}
}
else if ((BIOS_smpEnabled) || (Core_getId() == 0)) {
if (remoteProcId == InterruptDucati_hostProcId) {
/* HOST to VIDEO-M3 */
arg = REG32(MAILBOX_MESSAGE(HOST_TO_VIDEO));
REG32(MAILBOX_IRQSTATUS_CLR_VIDEO) = MAILBOX_REG_VAL(HOST_TO_VIDEO);
}
else {
/* DSP to VIDEO-M3 */
arg = REG32(MAILBOX_MESSAGE(DSP_TO_VIDEO));
REG32(MAILBOX_IRQSTATUS_CLR_VIDEO) = MAILBOX_REG_VAL(DSP_TO_VIDEO);
}
}
else { /* M3DSSINT */
if (remoteProcId == InterruptDucati_hostProcId) {
/* HOST to VPSS-M3 */
arg = REG32(MAILBOX_MESSAGE(HOST_TO_VPSS));
REG32(MAILBOX_IRQSTATUS_CLR_VPSS) = MAILBOX_REG_VAL(HOST_TO_VPSS);
}
else {
/* DSP to VPSS-M3 */
arg = REG32(MAILBOX_MESSAGE(DSP_TO_VPSS));
REG32(MAILBOX_IRQSTATUS_CLR_VPSS) = MAILBOX_REG_VAL(DSP_TO_VPSS);
}
}
return (arg);
}
/*!
* ======== InterruptDsp_intEnable ========
* Enable remote processor interrupt
*/
Void InterruptDsp_intEnable(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
if (remoteProcId == InterruptDsp_hostProcId) {
REG32(MAILBOX_IRQENABLE_SET_DSP) = MAILBOX_REG_VAL(HOST_TO_DSP);
}
else if (remoteProcId == InterruptDsp_videoProcId) {
REG32(MAILBOX_IRQENABLE_SET_DSP) = MAILBOX_REG_VAL(VIDEO_TO_DSP);
}
else if (remoteProcId == InterruptDsp_vpssProcId) {
REG32(MAILBOX_IRQENABLE_SET_DSP) = MAILBOX_REG_VAL(VPSS_TO_DSP);
}
else {
Assert_isTrue(FALSE, ti_sdo_ipc_Ipc_A_internal);
}
}
/*
* ======== InterruptEve_intEnable ========
* Enable remote processor interrupt
*/
Void InterruptEve_intEnable(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
if (remoteProcId == InterruptEve_hostProcId) {
REG32(MAILBOX_IRQENABLE_SET_EVE) = MAILBOX_REG_VAL(HOST_TO_EVE);
}
else if ((remoteProcId == InterruptEve_videoProcId) ||
(remoteProcId == InterruptEve_vpssProcId)) {
REG32(MAILBOX_IRQENABLE_SET_EVE) = MAILBOX_REG_VAL(VIDEO_TO_EVE);
}
else if (remoteProcId == InterruptEve_dspProcId) {
REG32(MAILBOX_IRQENABLE_SET_EVE) = MAILBOX_REG_VAL(DSP_TO_EVE);
}
else {
Assert_isTrue(FALSE, ti_sdo_ipc_Ipc_A_internal);
}
}
/*!
* ======== InterruptBenelli_intShmMbxStub ========
*/
Void InterruptBenelli_intShmMbxStub(UArg arg)
{
UInt16 index;
UInt16 selfIdx;
UInt16 loopIdx;
InterruptBenelli_FxnTable *table;
selfIdx = MultiProc_self();
for (loopIdx = 0; loopIdx < MultiProc_getNumProcsInCluster(); loopIdx++) {
if (loopIdx == selfIdx) {
continue;
}
index = MBX_TABLE_IDX(loopIdx, selfIdx);
if (((REG32(MAILBOX_STATUS(index)) != 0) &&
(REG32(MAILBOX_IRQENABLE_SET(index)) &
MAILBOX_REG_VAL(SUBMBX_IDX(index))))) {
table = &(InterruptBenelli_module->fxnTable[PROCID(loopIdx)]);
(table->func)(table->arg);
}
}
}
/*!
* ======== InterruptDsp_intShmStub ========
*/
Void InterruptDsp_intShmStub(UArg arg)
{
UInt16 index;
UInt16 selfIdx;
UInt16 loopIdx;
InterruptDsp_FxnTable *table;
selfIdx = MultiProc_self();
/*
* Loop through each Sub-mailbox to determine which one generated
* interrupt.
*/
for (loopIdx = 0; loopIdx < MultiProc_getNumProcsInCluster(); loopIdx++) {
if (loopIdx == selfIdx) {
continue;
}
index = MBX_TABLE_IDX(loopIdx, selfIdx);
if ((REG32(MAILBOX_STATUS(index)) != 0) &&
(REG32(MAILBOX_IRQENABLE_SET_DSP(index)) &
MAILBOX_REG_VAL(SUBMBX_IDX(index)))) {
table = &(InterruptDsp_module->fxnTable[PROCID(loopIdx)]);
(table->func)(table->arg);
}
}
}
/*!
* ======== InterruptArp32_intEnable ========
* Enable remote processor interrupt
*/
Void InterruptArp32_intEnable(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt16 index;
index = MBX_TABLE_IDX(remoteProcId, MultiProc_self());
REG32(MAILBOX_IRQENABLE_SET(index)) = MAILBOX_REG_VAL(SUBMBX_IDX(index));
}
/*
* ======== InterruptHost_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptHost_intDisable(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
if (remoteProcId == InterruptHost_dspProcId) {
REG32(MAILBOX_IRQENABLE_CLR_HOST) = MAILBOX_REG_VAL(DSP_TO_HOST);
}
else if (remoteProcId == InterruptHost_videoProcId) {
REG32(MAILBOX_IRQENABLE_CLR_HOST) = MAILBOX_REG_VAL(VIDEO_TO_HOST);
}
else if (remoteProcId == InterruptHost_vpssProcId) {
REG32(MAILBOX_IRQENABLE_CLR_HOST) = MAILBOX_REG_VAL(VPSS_TO_HOST);
}
else if (remoteProcId == InterruptHost_eveProcId) {
REG32(EVE_MAILBOX_IRQENABLE_CLR_HOST) = MAILBOX_REG_VAL(EVE_TO_HOST);
}
else {
Assert_isTrue(FALSE, ti_sdo_ipc_Ipc_A_internal);
}
}
/*!
* ======== InterruptBenelli_intClear ========
* Clear interrupt
*/
UInt InterruptBenelli_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
UInt16 index;
index = MBX_TABLE_IDX(remoteProcId, MultiProc_self());
arg = REG32(MAILBOX_MESSAGE(index));
REG32(MAILBOX_IRQSTATUS_CLR(index)) = MAILBOX_REG_VAL(SUBMBX_IDX(index));
return (arg);
}
/*!
* ======== InterruptDsp_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptDsp_intDisable(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt16 index;
Assert_isTrue(((remoteProcId < MultiProc_getNumProcsInCluster()) &&
(remoteProcId != MultiProc_self())), ti_sdo_ipc_Ipc_A_internal);
index = MBX_TABLE_IDX(remoteProcId, MultiProc_self());
REG32(MAILBOX_IRQENABLE_CLR_DSP(index)) = MAILBOX_REG_VAL(SUBMBX_IDX(index));
}
/*
* ======== InterruptHost_intEveShmStub ========
*/
Void InterruptHost_intEveShmStub(UArg arg)
{
InterruptHost_FxnTable *table;
/* Process messages from the EVE */
if ((REG32(EVE_MAILBOX_IRQENABLE_SET_HOST) & MAILBOX_REG_VAL(EVE_TO_HOST))
&& REG32(EVE_MAILBOX_STATUS(EVE_TO_HOST)) != 0) {
table = &(InterruptHost_module->fxnTable[3]);
(table->func)(table->arg);
}
}
/*!
* ======== InterruptBenelli_intEnable ========
* Enable remote processor interrupt
*/
Void InterruptBenelli_intEnable(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt16 index;
index = MBX_TABLE_IDX(remoteProcId, MultiProc_self());
/*
* If the remote processor communicates via mailboxes, we should enable
* the Mailbox IRQ instead of enabling the Hwi because multiple mailboxes
* share the same Hwi
*/
REG32(MAILBOX_IRQENABLE_SET(index)) = MAILBOX_REG_VAL(SUBMBX_IDX(index));
}
/*!
* ======== InterruptDsp_intShmStub ========
*/
Void InterruptDsp_intShmStub(UArg arg)
{
InterruptDsp_FxnTable *table;
if (((REG32(MAILBOX_IRQENABLE_SET(MBX_INTR_TO_DSP)) &
MAILBOX_REG_VAL(ARP32_TO_DSP)) &&
REG32(MAILBOX_STATUS(ARP32_TO_DSP))) != 0) {
/* call function with arg */
table = &(InterruptDsp_module->fxnTable);
(table->func)(table->arg);
}
}
/*!
* ======== InterruptArp32_intShmStub ========
*/
Void InterruptArp32_intShmStub(UArg arg)
{
InterruptArp32_FxnTable *table;
if ((REG32(MAILBOX_IRQENABLE_SET(MBX_INTR_TO_ARP32)) &
MAILBOX_REG_VAL(DSP_TO_ARP32)) &&
REG32(MAILBOX_STATUS(DSP_TO_ARP32)) != 0) { /* DSP to ARP32 */
/* call function with arg */
table = &(InterruptArp32_module->fxnTable);
(table->func)(table->arg);
}
}
/*!
* ======== InterruptArp32_intClear ========
* Clear interrupt
*/
UInt InterruptArp32_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
/* DSP to ARP32 */
arg = REG32(MAILBOX_MESSAGE(DSP_TO_ARP32));
/* clear the dsp mailbox */
REG32(MAILBOX_IRQSTATUS_CLR(MBX_INTR_TO_ARP32)) = MAILBOX_REG_VAL(DSP_TO_ARP32);
return (arg);
}
/*!
* ======== InterruptM3_intClear ========
* Clear interrupt and return payload
*/
UInt InterruptM3_intClear()
{
UInt arg = InterruptM3_INVALIDPAYLOAD;
/* First check whether incoming mailbox has a message */
if (Core_getId() == 0) {
/* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */
if (REG32(MAILBOX_STATUS(SYSM3_MBX)) == 0) {
return (arg);
}
else {
/* If there is a message, return the argument to the caller */
arg = REG32(MAILBOX_MESSAGE(SYSM3_MBX));
REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(SYSM3_MBX);
}
}
else {
/* Clear the inter-M3 interrupt if necessary */
if ((REG16(INTERRUPT_CORE_1) & 0x1) == 0x1) {
REG16(INTERRUPT_CORE_1) &= ~(0x1);
}
/* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */
if (REG32(MAILBOX_STATUS(APPM3_MBX)) == 0) {
return (arg);
}
else {
/* If there is a message, return the argument to the caller */
arg = REG32(MAILBOX_MESSAGE(APPM3_MBX));
REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(APPM3_MBX);
if (REG32(MAILBOX_STATUS(APPM3_MBX)) != 0) {
/* Trigger our own interrupt since another interrupt pending */
REG16(INTERRUPT_CORE_1) |= 0x1;
}
}
}
return (arg);
}
/*!
* ======== InterruptDsp_intClear ========
* Clear interrupt
*/
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
if (remoteProcId == InterruptDsp_hostProcId) {
arg = REG32(MAILBOX_MESSAGE(HOST_TO_DSP));
REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(HOST_TO_DSP);
}
else if (remoteProcId == InterruptDsp_videoProcId) {
arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP));
REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(VIDEO_TO_DSP);
}
else { /* VPSS-M3 */
arg = REG32(MAILBOX_MESSAGE(VPSS_TO_DSP));
REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(VPSS_TO_DSP);
}
/* Write to EOI (End Of Interrupt) register */
REG32(MAILBOX_EOI_REG) = 0x1;
return (arg);
}
/*!
* ======== InterruptDsp_intClear ========
* Clear interrupt
*/
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
arg = REG32(MAILBOX_MESSAGE(ARP32_TO_DSP));
/* clear the dsp mailbox */
REG32(MAILBOX_IRQSTATUS_CLR(MBX_INTR_TO_DSP)) = MAILBOX_REG_VAL(ARP32_TO_DSP);
/* Write to EOI (End Of Interrupt) register */
REG32(MAILBOX_EOI_REG) = 0x1;
return (arg);
}
/*
* ======== InterruptEve_intClear ========
* Clear interrupt
*/
UInt InterruptEve_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
if (remoteProcId == InterruptEve_hostProcId) { /* HOST */
arg = REG32(MAILBOX_MESSAGE(HOST_TO_EVE));
REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(HOST_TO_EVE);
}
else if ((remoteProcId == InterruptEve_videoProcId) || /* VIDEO-M3 */
(remoteProcId == InterruptEve_vpssProcId)) {
arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_EVE));
REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(VIDEO_TO_EVE);
}
else { /* DSP */
arg = REG32(MAILBOX_MESSAGE(DSP_TO_EVE));
REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(DSP_TO_EVE);
}
/* Write to EOI (End Of Interrupt) register */
REG32(MAILBOX_EOI_REG) = 0x1;
return (arg);
}
/*!
* ======== InterruptM3_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptM3_intDisable()
{
/*
* If the remote processor communicates via mailboxes, we should disable
* the Mailbox IRQ instead of disabling the Hwi because multiple mailboxes
* share the same Hwi
*/
if (Core_getId() == 0) {
REG32(MAILBOX_IRQENABLE_CLR_M3) = MAILBOX_REG_VAL(SYSM3_MBX);
}
else {
Hwi_disableInterrupt(M3INT);
}
}
/*!
* ======== InterruptDsp_intClear ========
* Clear interrupt
*/
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
UInt16 index;
index = MBX_TABLE_IDX(remoteProcId, MultiProc_self());
arg = REG32(MAILBOX_MESSAGE(index));
REG32(MAILBOX_IRQSTATUS_CLR_DSP(index)) = MAILBOX_REG_VAL(SUBMBX_IDX(index));
/* Write to EOI (End Of Interrupt) register */
REG32(MAILBOX_EOI_REG(index)) = 0x1;
return (arg);
}
/*!
* ======== InterruptIpu_intClear ========
* Clear interrupt and return payload
*/
UInt InterruptIpu_intClear()
{
UInt arg = INVALIDPAYLOAD;
/* If FIFO is empty, return INVALIDPAYLOAD */
if (REG32(MAILBOX_STATUS(HOST_TO_SYSM3_MBX)) == 0) {
return (arg);
}
else {
/* If there is a message, return the argument to the caller */
arg = REG32(MAILBOX_MESSAGE(HOST_TO_SYSM3_MBX));
REG32(MAILBOX_IRQSTATUS_CLR_M3) =
MAILBOX_REG_VAL(HOST_TO_SYSM3_MBX);
}
return (arg);
}
/*!
* ======== InterruptDsp_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptDsp_intDisable(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
REG32(MAILBOX_IRQENABLE_CLR(MBX_INTR_TO_DSP)) = MAILBOX_REG_VAL(ARP32_TO_DSP);
}
/*!
* ======== InterruptIpu_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptIpu_intDisable()
{
REG32(MAILBOX_IRQENABLE_CLR_M3) = MAILBOX_REG_VAL(HOST_TO_SYSM3_MBX);
}
/*!
* ======== InterruptArp32_intDisable ========
* Disables remote processor interrupt
*/
Void InterruptArp32_intDisable(UInt16 remoteProcId,
IInterrupt_IntInfo *intInfo)
{
REG32(MAILBOX_IRQENABLE_CLR(MBX_INTR_TO_ARP32)) = MAILBOX_REG_VAL(DSP_TO_ARP32);
Hwi_disableInterrupt(ARP32INT);
}
