static inline void
rawhide_update_irq_hw(int hose, int mask)
{
*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask;
mb();
*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose));
}
static void __init
rawhide_init_irq(void)
{
struct pci_controller *hose;
long i;
mcpcia_init_hoses();
/* Clear them all; only hoses that exist will be non-zero. */
for (i = 0; i < MCPCIA_MAX_HOSES; i++) cached_irq_masks[i] = 0;
for (hose = hose_head; hose; hose = hose->next) {
unsigned int h = hose->index;
unsigned int mask = hose_irq_masks[h];
cached_irq_masks[h] = mask;
*(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask;
*(vuip)MCPCIA_INT_MASK1(MCPCIA_HOSE2MID(h)) = 0;
}
for (i = 16; i < 128; ++i) {
irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
irq_desc[i].chip = &rawhide_irq_type;
}
init_i8259a_irqs();
common_init_isa_dma();
}
static void
rawhide_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
{
if (irq >= 40) {
/* PCI bus 1 with builtin NCR810 SCSI */
*(vuip)MCPCIA_INT_MASK0(1) =
(~((mask) >> 40) & 0x00ffffffU) | 0x00fe0000U;
mb();
/* ... and read it back to make sure it got written. */
*(vuip)MCPCIA_INT_MASK0(1);
}
