static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
{
static const uint32_t code[] = {
/* start: */
MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
MIPS32_SW(8,0,15), /* sw $8,($15) */
MIPS32_SW(9,0,15), /* sw $9,($15) */
MIPS32_SW(10,0,15), /* sw $10,($15) */
MIPS32_SW(11,0,15), /* sw $11,($15) */
MIPS32_ADDI(8,15,NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN)), /* $8= MIPS32_PRACC_PARAM_IN */
MIPS32_LW(9,0,8), /* Load write addr to $9 */
MIPS32_LW(10,4,8), /* Load write count to $10 */
MIPS32_ADDI(8,8,8), /* $8 += 8 beginning of data */
/* loop: */
MIPS32_LW(11,0,8), /* lw $11,0($8), Load $11 with the word @mem[$8] */
MIPS32_SW(11,0,9), /* sw $11,0($9) */
MIPS32_ADDI(9,9,4), /* $9 += 4 */
MIPS32_BNE(10,9,NEG16(4)), /* bne $10, $9, loop */
MIPS32_ADDI(8,8,4), /* $8 += 4 */
/* end: */
MIPS32_LW(11,0,15), /* lw $11,($15) */
MIPS32_LW(10,0,15), /* lw $10,($15) */
MIPS32_LW(9,0,15), /* lw $9,($15) */
MIPS32_LW(8,0,15), /* lw $8,($15) */
MIPS32_B(NEG16(21)), /* b start */
MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
};
/* TODO remove array */
uint32_t *param_in = malloc((count + 2) * sizeof(uint32_t));
param_in[0] = addr;
param_in[1] = addr + (count * sizeof(uint32_t)); /* last address */
memcpy(¶m_in[2], buf, count * sizeof(uint32_t));
int retval;
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
count + 2, param_in, 0, NULL, 1);
free(param_in);
return retval;
}
/**
* \b mips32_pracc_sync_cache
*
* Synchronize Caches to Make Instruction Writes Effective
* (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set,
* Document Number: MD00086, Revision 2.00, June 9, 2003)
*
* When the instruction stream is written, the SYNCI instruction should be used
* in conjunction with other instructions to make the newly-written instructions effective.
*
* Explanation :
* A program that loads another program into memory is actually writing the D- side cache.
* The instructions it has loaded can't be executed until they reach the I-cache.
*
* After the instructions have been written, the loader should arrange
* to write back any containing D-cache line and invalidate any locations
* already in the I-cache.
*
* You can do that with cache instructions, but those instructions are only available in kernel mode,
* and a loader writing instructions for the use of its own process need not be privileged software.
*
* In the latest MIPS32/64 CPUs, MIPS provides the synci instruction,
* which does the whole job for a cache-line-sized chunk of the memory you just loaded:
* That is, it arranges a D-cache write-back and an I-cache invalidate.
*
* To employ synci at user level, you need to know the size of a cache line,
* and that can be obtained with a rdhwr SYNCI_Step
* from one of the standard “hardware registers”.
*/
static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info,
uint32_t start_addr, uint32_t end_addr)
{
static const uint32_t code[] = {
/* start: */
MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
MIPS32_SW(8, 0, 15), /* sw $8,($15) */
MIPS32_SW(9, 0, 15), /* sw $9,($15) */
MIPS32_SW(10, 0, 15), /* sw $10,($15) */
MIPS32_SW(11, 0, 15), /* sw $11,($15) */
MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */
MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)),
MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */
MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */
MIPS32_RDHWR(11, MIPS32_SYNCI_STEP), /* $11 = MIPS32_SYNCI_STEP */
MIPS32_BEQ(11, 0, 6), /* beq $11, $0, end */
MIPS32_NOP,
/* synci_loop : */
MIPS32_SYNCI(0, 9), /* synci 0($9) */
MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */
MIPS32_BNE(8, 0, NEG16(3)), /* bne $8, $0, synci_loop */
MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */
MIPS32_SYNC,
/* end: */
MIPS32_LW(11, 0, 15), /* lw $11,($15) */
MIPS32_LW(10, 0, 15), /* lw $10,($15) */
MIPS32_LW(9, 0, 15), /* lw $9,($15) */
MIPS32_LW(8, 0, 15), /* lw $8,($15) */
MIPS32_B(NEG16(24)), /* b start */
MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
};
/* TODO remove array */
uint32_t *param_in = malloc(2 * sizeof(uint32_t));
int retval;
param_in[0] = start_addr;
param_in[1] = end_addr;
retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 2, param_in, 0, NULL, 1);
free(param_in);
return retval;
}
/* fastdata upload/download requires an initialized working area
* to load the download code; it should not be called otherwise
* fetch order from the fastdata area
* 1. start addr
* 2. end addr
* 3. data ...
*/
int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
int write, uint32_t addr, int count, uint32_t *buf)
{
uint32_t handler_code[] = {
/* caution when editing, table is modified below */
/* r15 points to the start of this code */
MIPS32_SW(8,MIPS32_FASTDATA_HANDLER_SIZE - 4,15),
MIPS32_SW(9,MIPS32_FASTDATA_HANDLER_SIZE - 8,15),
MIPS32_SW(10,MIPS32_FASTDATA_HANDLER_SIZE - 12,15),
MIPS32_SW(11,MIPS32_FASTDATA_HANDLER_SIZE - 16,15),
/* start of fastdata area in t0 */
MIPS32_LUI(8,UPPER16(MIPS32_PRACC_FASTDATA_AREA)),
MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_FASTDATA_AREA)),
MIPS32_LW(9,0,8), /* start addr in t1 */
MIPS32_LW(10,0,8), /* end addr to t2 */
/* loop: */
/* 8 */ MIPS32_LW(11,0,0), /* lw t3,[t8 | r9] */
/* 9 */ MIPS32_SW(11,0,0), /* sw t3,[r9 | r8] */
MIPS32_BNE(10,9,NEG16(3)), /* bne $t2,t1,loop */
MIPS32_ADDI(9,9,4), /* addi t1,t1,4 */
MIPS32_LW(8,MIPS32_FASTDATA_HANDLER_SIZE - 4,15),
MIPS32_LW(9,MIPS32_FASTDATA_HANDLER_SIZE - 8,15),
MIPS32_LW(10,MIPS32_FASTDATA_HANDLER_SIZE - 12,15),
MIPS32_LW(11,MIPS32_FASTDATA_HANDLER_SIZE - 16,15),
MIPS32_LUI(15,UPPER16(MIPS32_PRACC_TEXT)),
MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_TEXT)),
MIPS32_JR(15), /* jr start */
MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */
};
uint32_t jmp_code[] = {
MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */
/* 1 */ MIPS32_LUI(15,0), /* addr of working area added below */
/* 2 */ MIPS32_ORI(15,15,0), /* addr of working area added below */
MIPS32_JR(15), /* jump to ram program */
MIPS32_NOP,
};
int retval, i;
uint32_t val, ejtag_ctrl, address;
if (source->size < MIPS32_FASTDATA_HANDLER_SIZE)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
if (write)
{
handler_code[8] = MIPS32_LW(11,0,8); /* load data from probe at fastdata area */
handler_code[9] = MIPS32_SW(11,0,9); /* store data to RAM @ r9 */
}
else
{
handler_code[8] = MIPS32_LW(11,0,9); /* load data from RAM @ r9 */
handler_code[9] = MIPS32_SW(11,0,8); /* store data to probe at fastdata area */
}
/* write program into RAM */
mips32_pracc_write_mem32(ejtag_info, source->address, ARRAY_SIZE(handler_code), handler_code);
LOG_DEBUG("%s using 0x%.8" PRIx32 " for write handler\n", __func__, source->address);
jmp_code[1] |= UPPER16(source->address);
jmp_code[2] |= LOWER16(source->address);
for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++)
{
if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
return retval;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
mips_ejtag_drscan_32(ejtag_info, &jmp_code[i]);
/* Clear the access pending bit (let the processor eat!) */
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
}
if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
return retval;
/* next fetch to dmseg should be in FASTDATA_AREA, check */
address = 0;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &address);
if (address != MIPS32_PRACC_FASTDATA_AREA)
return ERROR_FAIL;
/* Send the load start address */
val = addr;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
/* Send the load end address */
val = addr + (count - 1) * 4;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL);
mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
for (i = 0; i < count; i++)
{
/* Send the data out using fastdata (clears the access pending bit) */
if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write, buf++)) != ERROR_OK)
return retval;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("fastdata load failed");
return retval;
}
if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
return retval;
address = 0;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
mips_ejtag_drscan_32(ejtag_info, &address);
if (address != MIPS32_PRACC_TEXT)
LOG_ERROR("mini program did not return to start\n");
return retval;
}
