static int
mpic_intr(void *arg)
{
struct mv_mpic_softc *sc;
struct trapframe *tf;
struct intr_irqsrc *isrc;
uint32_t cause, irqsrc;
unsigned int irq;
u_int cpuid;
sc = arg;
tf = curthread->td_intr_frame;
cpuid = PCPU_GET(cpuid);
irq = 0;
for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0;
cause >>= 1, irq++) {
if (cause & 1) {
irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq));
if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0)
continue;
isrc = sc->mpic_isrcs[irq];
if (isrc == NULL) {
device_printf(sc->sc_dev, "Stray interrupt %u detected\n", irq);
mpic_mask_irq(irq);
continue;
}
intr_irq_dispatch(isrc, tf);
}
}
return (FILTER_HANDLED);
}
static int
mpic_intr(void *arg)
{
struct mv_mpic_softc *sc;
uint32_t cause, irqsrc;
unsigned int irq;
u_int cpuid;
sc = arg;
cpuid = PCPU_GET(cpuid);
irq = 0;
for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0;
cause >>= 1, irq++) {
if (cause & 1) {
irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq));
if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0)
continue;
if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc,
curthread->td_intr_frame) != 0) {
mpic_mask_irq(irq);
device_printf(sc->sc_dev, "Stray irq %u "
"disabled\n", irq);
}
}
}
return (FILTER_HANDLED);
}
static int
mv_mpic_attach(device_t dev)
{
struct mv_mpic_softc *sc;
int error;
uint32_t val;
sc = (struct mv_mpic_softc *)device_get_softc(dev);
if (mv_mpic_sc != NULL)
return (ENXIO);
mv_mpic_sc = sc;
sc->sc_dev = dev;
mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN);
error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
if (error) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
#ifdef ARM_INTRNG
if (sc->mpic_res[3] == NULL)
device_printf(dev, "No interrupt to use.\n");
else
bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
mpic_intr, NULL, sc, &sc->intr_hand);
#endif
sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
if (sc->mpic_res[2] != NULL) {
/* This is required only if MSIs are used. */
sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
}
bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
MPIC_CTRL, 1);
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
sc->nirqs = MPIC_CTRL_NIRQS(val);
#ifdef ARM_INTRNG
sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF,
M_WAITOK | M_ZERO);
if (intr_pic_register(dev, OF_xref_from_device(dev)) != 0) {
device_printf(dev, "could not register PIC\n");
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
return (ENXIO);
}
#endif
mpic_unmask_msi();
return (0);
}
