Exemple #1
0
/*
 * set_access_control - Config address decode parameters for Ethernet unit
 *
 * This function configures the address decode parameters for the Gigabit
 * Ethernet Controller according the given parameters struct.
 *
 * @regs	Register struct pointer.
 * @param	Address decode parameter struct.
 */
static void set_access_control(struct mvgbe_registers *regs,
				struct mvgbe_winparam *param)
{
	u32 access_prot_reg;

	/* Set access control register */
	access_prot_reg = MVGBE_REG_RD(regs->epap);
	/* clear window permission */
	access_prot_reg &= (~(3 << (param->win * 2)));
	access_prot_reg |= (param->access_ctrl << (param->win * 2));
	MVGBE_REG_WR(regs->epap, access_prot_reg);

	/* Set window Size reg (SR) */
	MVGBE_REG_WR(regs->barsz[param->win].size,
			(((param->size / 0x10000) - 1) << 16));

	/* Set window Base address reg (BA) */
	MVGBE_REG_WR(regs->barsz[param->win].bar,
			(param->target | param->attrib | param->base_addr));
	/* High address remap reg (HARR) */
	if (param->win < 4)
		MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);

	/* Base address enable reg (BARER) */
	if (param->enable == 1)
		MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
	else
		MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
}
Exemple #2
0
static int mvgbe_init(struct eth_device *dev)
{
    struct mvgbe_device *dmvgbe = to_mvgbe(dev);
    struct mvgbe_registers *regs = dmvgbe->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
    int i;
#endif
    /* setup RX rings */
    mvgbe_init_rx_desc_ring(dmvgbe);

    /* Clear the ethernet port interrupts */
    MVGBE_REG_WR(regs->ic, 0);
    MVGBE_REG_WR(regs->ice, 0);
    /* Unmask RX buffer and TX end interrupt */
    MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
    /* Unmask phy and link status changes interrupts */
    MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);

    set_dram_access(regs);
    port_init_mac_tables(regs);
    port_uc_addr_set(regs, dmvgbe->dev.enetaddr);

    /* Assign port configuration and command. */
    MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
    MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
    MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);

    /* Assign port SDMA configuration */
    MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
    MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
    MVGBE_REG_WR(regs->tqx[0].tqxtbc,
                 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
    /* Turn off the port/RXUQ bandwidth limitation */
    MVGBE_REG_WR(regs->pmtu, 0);

    /* Set maximum receive buffer to 9700 bytes */
    MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
                 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));

    /* Enable port initially */
    MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);

    /*
     * Set ethernet MTU for leaky bucket mechanism to 0 - this will
     * disable the leaky bucket mechanism .
     */
    MVGBE_REG_WR(regs->pmtu, 0);

    /* Assignment of Rx CRDB of given RXUQ */
    MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
    /* ensure previous write is done before enabling Rx DMA */
    isb();
    /* Enable port Rx. */
    MVGBE_REG_WR(regs->rqc, (1 << RXUQ));

#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
    /* Wait up to 5s for the link status */
    for (i = 0; i < 5; i++) {
        u16 phyadr;

        miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
                    MV_PHY_ADR_REQUEST, &phyadr);
        /* Return if we get link up */
        if (miiphy_link(dev->name, phyadr))
            return 0;
        udelay(1000000);
    }

    printf("No link on %s\n", dev->name);
    return -1;
#endif
    return 0;
}