void mxr_reg_layer_alpha(struct mxr_device *mdev, int sub_mxr, int num, u32 a)
{
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_VIDEO)
mxr_write_mask(mdev, MXR_VIDEO_CFG, MXR_VIDEO_CFG_ALPHA(a),
0xff);
else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0)
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0), MXR_GRP_CFG_ALPHA_VAL(a),
0xff);
else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1)
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1), MXR_GRP_CFG_ALPHA_VAL(a),
0xff);
#if defined(CONFIG_ARCH_EXYNOS5)
else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_VIDEO)
mxr_write_mask(mdev, MXR1_VIDEO_CFG, MXR_VIDEO_CFG_ALPHA(a),
0xff);
else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0)
mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0), MXR_GRP_CFG_ALPHA_VAL(a),
0xff);
else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1)
mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1), MXR_GRP_CFG_ALPHA_VAL(a),
0xff);
#endif
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_set_layer_blend(struct mxr_device *mdev, int sub_mxr, int num,
int en)
{
u32 val = en ? ~0 : 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_VIDEO)
mxr_write_mask(mdev, MXR_VIDEO_CFG, val,
MXR_VIDEO_CFG_BLEND_EN);
else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP0)
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0), val,
MXR_GRP_CFG_LAYER_BLEND_EN);
else if (sub_mxr == MXR_SUB_MIXER0 && num == MXR_LAYER_GRP1)
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1), val,
MXR_GRP_CFG_LAYER_BLEND_EN);
#if defined(CONFIG_ARCH_EXYNOS5)
else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_VIDEO)
mxr_write_mask(mdev, MXR1_VIDEO_CFG, val,
MXR_VIDEO_CFG_BLEND_EN);
else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP0)
mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0), val,
MXR_GRP_CFG_LAYER_BLEND_EN);
else if (sub_mxr == MXR_SUB_MIXER1 && num == MXR_LAYER_GRP1)
mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1), val,
MXR_GRP_CFG_LAYER_BLEND_EN);
#endif
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_layer_blend_alpha(struct mxr_device *mdev , int idx, u32 en)
{
unsigned long flags;
int val;
spin_lock_irqsave(&mdev->reg_slock, flags);
val = mxr_read(mdev,MXR_GRAPHIC_CFG(idx));
BF_SET(val,en,0,8);
mxr_write(mdev, MXR_GRAPHIC_CFG(idx),val);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
static void mxr_reg_sub_mxr_reset(struct mxr_device *mdev, int mxr_num)
{
u32 val; /* value stored to register */
if (mxr_num == MXR_SUB_MIXER0) {
/* setting default layer priority: layer1 > video > layer0
* because typical usage scenario would be
* layer0 - framebuffer
* video - video overlay
* layer1 - OSD
*/
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
mxr_write(mdev, MXR_LAYER_CFG, val);
/* use dark gray background color */
mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
} else if (mxr_num == MXR_SUB_MIXER1) {
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
mxr_write(mdev, MXR1_LAYER_CFG, val);
/* use dark gray background color */
mxr_write(mdev, MXR1_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR1_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR1_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR1_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR1_GRAPHIC_CFG(1), val);
}
}
void mxr_reg_reset(struct mxr_device *mdev)
{
unsigned long flags;
u32 val; /* value stored to register */
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* set output in RGB888 mode */
mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
/* 16 beat burst in DMA */
mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
MXR_STATUS_BURST_MASK);
/* setting default layer priority: layer1 > video > layer0
* because typical usage scenario would be
* layer0 - framebuffer
* video - video overlay
* layer1 - OSD
*/
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
mxr_write(mdev, MXR_LAYER_CFG, val);
/* use dark teal background color */
mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
val |= MXR_GRP_CFG_LAYER_BLEND_EN;
val &= ~MXR_GRP_CFG_BLEND_PRE_MUL; /* normal mode */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
/* configuration of Video Processor Registers */
__mxr_reg_vp_reset(mdev);
mxr_reg_vp_default_filter(mdev);
/* enable all interrupts */
mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_chromakey_enable(struct mxr_device *mdev, int idx,u32 en)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
val=(u32)mxr_read(mdev,MXR_GRAPHIC_CFG(idx));
if (en)
val &= ~MXR_GRP_CFG_COLOR_KEY_DISABLE;
else
val |= MXR_GRP_CFG_COLOR_KEY_DISABLE;
mxr_write(mdev,MXR_GRAPHIC_CFG(idx),val);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_format(struct mxr_device *mdev, int idx,
const struct mxr_format *fmt, const struct mxr_geometry *geo)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* setup format */
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(idx),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie), MXR_GRP_CFG_FORMAT_MASK);
/* setup geometry */
mxr_write(mdev, MXR_GRAPHIC_SPAN(idx), geo->src.full_width);
val = MXR_GRP_WH_WIDTH(geo->src.width);
val |= MXR_GRP_WH_HEIGHT(geo->src.height);
val |= MXR_GRP_WH_H_SCALE(geo->x_ratio);
val |= MXR_GRP_WH_V_SCALE(geo->y_ratio);
mxr_write(mdev, MXR_GRAPHIC_WH(idx), val);
/* setup offsets in source image */
val = MXR_GRP_SXY_SX(geo->src.x_offset);
val |= MXR_GRP_SXY_SY(geo->src.y_offset);
mxr_write(mdev, MXR_GRAPHIC_SXY(idx), val);
/* setup offsets in display image */
val = MXR_GRP_DXY_DX(geo->dst.x_offset);
val |= MXR_GRP_DXY_DY(geo->dst.y_offset);
mxr_write(mdev, MXR_GRAPHIC_DXY(idx), val);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_reset(struct mxr_device *mdev)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
MXR_STATUS_BURST_MASK);
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
mxr_write(mdev, MXR_LAYER_CFG, val);
mxr_write(mdev, MXR_BG_COLOR0, 0x808080);
mxr_write(mdev, MXR_BG_COLOR1, 0x808080);
mxr_write(mdev, MXR_BG_COLOR2, 0x808080);
val = MXR_GRP_CFG_COLOR_KEY_DISABLE;
val |= MXR_GRP_CFG_BLEND_PRE_MUL;
val |= MXR_GRP_CFG_ALPHA_VAL(0xff);
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
__mxr_reg_vp_reset(mdev);
mxr_reg_vp_default_filter(mdev);
mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
void mxr_reg_graph_pixel_blend_enable(struct mxr_device *mdev , int idx, u32 en)
{
u32 val = en ? ~0 : 0;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(idx), val , MXR_GRP_CFG_PIXEL_BLEND_EN);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
static void mxr_reg_sub_mxr_reset(struct mxr_device *mdev, int mxr_num)
{
u32 val; /* value stored to register */
if (mxr_num == MXR_SUB_MIXER0) {
/* use dark gray background color */
mxr_write(mdev, MXR_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_BLANK_KEY_EN; /* no blank key */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
} else if (mxr_num == MXR_SUB_MIXER1) {
val = MXR_LAYER_CFG_GRP1_VAL(3);
val |= MXR_LAYER_CFG_GRP0_VAL(2);
val |= MXR_LAYER_CFG_VP_VAL(1);
mxr_write(mdev, MXR1_LAYER_CFG, val);
/* use dark gray background color */
mxr_write(mdev, MXR1_BG_COLOR0, 0x008080);
mxr_write(mdev, MXR1_BG_COLOR1, 0x008080);
mxr_write(mdev, MXR1_BG_COLOR2, 0x008080);
/* setting graphical layers */
val = MXR_GRP_CFG_BLANK_KEY_EN; /* no blank key */
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
/* the same configuration for both layers */
mxr_write(mdev, MXR1_GRAPHIC_CFG(0), val);
mxr_write(mdev, MXR1_GRAPHIC_CFG(1), val);
}
}
void mxr_reg_graph_format(struct mxr_device *mdev, int idx,
const struct mxr_format *fmt, const struct mxr_geometry *geo)
{
u32 wh, sxy, dxy;
unsigned long flags;
spin_lock_irqsave(&mdev->reg_slock, flags);
mxr_vsync_set_update(mdev, MXR_DISABLE);
/* Mostly, src width, height and dst width, height are same.
* However, in case of doing src and dst cropping, those are different.
* So you have to write dst width and height to MXR_GRAPHIC_WH register.
*/
wh = MXR_GRP_WH_WIDTH(geo->dst.width);
wh |= MXR_GRP_WH_HEIGHT(geo->dst.height);
wh |= MXR_GRP_WH_H_SCALE(geo->x_ratio);
wh |= MXR_GRP_WH_V_SCALE(geo->y_ratio);
/* setup offsets in source image */
sxy = MXR_GRP_SXY_SX(geo->src.x_offset);
sxy |= MXR_GRP_SXY_SY(geo->src.y_offset);
/* setup offsets in display image */
dxy = MXR_GRP_DXY_DX(geo->dst.x_offset);
dxy |= MXR_GRP_DXY_DY(geo->dst.y_offset);
if (idx == 0) {
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(0),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
MXR_GRP_CFG_FORMAT_MASK);
mxr_write(mdev, MXR_GRAPHIC_SPAN(0), geo->src.full_width);
mxr_write(mdev, MXR_GRAPHIC_WH(0), wh);
mxr_write(mdev, MXR_GRAPHIC_SXY(0), sxy);
mxr_write(mdev, MXR_GRAPHIC_DXY(0), dxy);
} else if (idx == 1) {
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(1),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
MXR_GRP_CFG_FORMAT_MASK);
mxr_write(mdev, MXR_GRAPHIC_SPAN(1), geo->src.full_width);
mxr_write(mdev, MXR_GRAPHIC_WH(1), wh);
mxr_write(mdev, MXR_GRAPHIC_SXY(1), sxy);
mxr_write(mdev, MXR_GRAPHIC_DXY(1), dxy);
} else if (idx == 2) {
mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(0),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
MXR_GRP_CFG_FORMAT_MASK);
mxr_write(mdev, MXR1_GRAPHIC_SPAN(0), geo->src.full_width);
mxr_write(mdev, MXR1_GRAPHIC_WH(0), wh);
mxr_write(mdev, MXR1_GRAPHIC_SXY(0), sxy);
mxr_write(mdev, MXR1_GRAPHIC_DXY(0), dxy);
} else if (idx == 3) {
mxr_write_mask(mdev, MXR1_GRAPHIC_CFG(1),
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie),
MXR_GRP_CFG_FORMAT_MASK);
mxr_write(mdev, MXR1_GRAPHIC_SPAN(1), geo->src.full_width);
mxr_write(mdev, MXR1_GRAPHIC_WH(1), wh);
mxr_write(mdev, MXR1_GRAPHIC_SXY(1), sxy);
mxr_write(mdev, MXR1_GRAPHIC_DXY(1), dxy);
}
mxr_vsync_set_update(mdev, MXR_ENABLE);
spin_unlock_irqrestore(&mdev->reg_slock, flags);
}
