void alpha8201_cpu_device::state_import(const device_state_entry &entry)
{
switch (entry.index())
{
case ALPHA8201_PC:
m_PREVPC = m_pc.w.l;
break;
case STATE_GENPCBASE:
m_pc.w.l = m_PREVPC;
break;
case STATE_GENFLAGS:
m_cf = BIT(m_flags, 1);
m_zf = BIT(m_flags, 0);
break;
case ALPHA8201_SP:
case STATE_GENSP:
M_WRMEM(0x001, m_sp);
break;
case ALPHA8201_R0:
WR_REG(0, m_R[0]);
break;
case ALPHA8201_R1:
WR_REG(1, m_R[1]);
break;
case ALPHA8201_R2:
WR_REG(2, m_R[2]);
break;
case ALPHA8201_R3:
WR_REG(3, m_R[3]);
break;
case ALPHA8201_R4:
WR_REG(4, m_R[4]);
break;
case ALPHA8201_R5:
WR_REG(5, m_R[5]);
break;
case ALPHA8201_R6:
WR_REG(6, m_R[6]);
break;
case ALPHA8201_R7:
WR_REG(7, m_R[7]);
break;
}
}
void alpha8201_cpu_device::state_import(const device_state_entry &entry)
{
switch (entry.index())
{
case ALPHA8201_SP:
M_WRMEM(0x001, m_sp);
break;
case ALPHA8201_R0:
WR_REG(0, m_R[0]);
break;
case ALPHA8201_R1:
WR_REG(1, m_R[1]);
break;
case ALPHA8201_R2:
WR_REG(2, m_R[2]);
break;
case ALPHA8201_R3:
WR_REG(3, m_R[3]);
break;
case ALPHA8201_R4:
WR_REG(4, m_R[4]);
break;
case ALPHA8201_R5:
WR_REG(5, m_R[5]);
break;
case ALPHA8201_R6:
WR_REG(6, m_R[6]);
break;
case ALPHA8201_R7:
WR_REG(7, m_R[7]);
break;
}
}
void alpha8201_cpu_device::execute_run()
{
unsigned opcode;
UINT8 pcptr;
if(m_halt)
{
m_icount = 0;
return;
}
/* setup address bank & fall safe */
m_ix0.b.h =
m_ix1.b.h =
m_ix2.b.h = (m_pc.b.h &= 3);
/* reset start hack */
if(m_pc.w.l<0x20)
m_mb |= 0x08;
do
{
if(m_mb & 0x08)
{
pcptr = M_RDMEM(0x001) & 0x1f; /* pointer of entry point */
m_icount -= C1;
/* entry point scan phase */
if( (pcptr&1) == 0)
{
/* EVEN , get PC low */
m_pc.b.l = M_RDMEM(pcptr);
//osd_printf_debug("alpha8201 load PCL ENTRY=%02X PCL=%02X\n",pcptr, m_pc.b.l);
m_icount -= C1;
M_WRMEM(0x001,pcptr+1);
continue;
}
/* ODD , check HALT flag */
m_mb = M_RDMEM(pcptr) & (0x08|0x03);
m_icount -= C1;
/* not entryaddress 000,001 */
if(pcptr<2) m_mb |= 0x08;
if(m_mb & 0x08)
{
/* HALTED current entry point . next one */
pcptr = (pcptr+1)&0x1f;
M_WRMEM(0x001,pcptr);
m_icount -= C1;
continue;
}
/* goto run phase */
M_JMP(m_pc.b.l);
#if SHOW_ENTRY_POINT
logerror("alpha8201 START ENTRY=%02X PC=%03X\n",pcptr,m_pc.w.l);
osd_printf_debug("alpha8201 START ENTRY=%02X PC=%03X\n",pcptr,m_pc.w.l);
#endif
}
/* run */
m_PREVPC = m_pc.w.l;
debugger_instruction_hook(this, m_pc.w.l);
opcode =M_RDOP(m_pc.w.l);
#if TRACE_PC
osd_printf_debug("alpha8201: PC = %03x, opcode = %02x\n", m_pc.w.l, opcode);
#endif
m_pc.b.l++;
m_inst_cycles = m_opmap[opcode].cycles;
(this->*m_opmap[opcode].opcode_func)();
m_icount -= m_inst_cycles;
} while (m_icount>0);
}
void alpha8201_cpu_device::stop()
{
UINT8 pcptr = M_RDMEM(0x001) & 0x1f;
M_WRMEM(pcptr,(M_RDMEM(pcptr)&0xf)+0x08); /* mark entry point ODD to HALT */
m_mb |= 0x08; /* mark internal HALT state */
}
static void wr_slow( int addr, int v )
{
M_WRMEM(addr,v);
}
